Table of Contents

• NEMESYS: near-memory graph copy enhanced system-softwareSven Rheindt, Andreas Fried, Oliver Lenke, Lars Nolte, Thomas Wild, Andreas Herkersdorf. 3-18 [doi]
• A computation-in-memory accelerator based on resistive devicesHoang Anh Du Nguyen, Jintao Yu, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui. 19-32 [doi]
• Attacking memory-hard scrypt with near-data-processingJiwon Choe, Tali Moreshet, R. Iris Bahar, Maurice Herlihy. 33-37 [doi]
• Digital-based processing in-memory: a highly-parallel accelerator for data intensive applicationsMohsen Imani, Saransh Gupta, Tajana Rosing. 38-40 [doi]
• PIMS: a lightweight processing-in-memory accelerator for stencil computationsJie Li, Xi Wang 0009, Antonino Tumeo, Brody Williams, John D. Leidel, Yong Chen 0001. 41-52 [doi]
• Fast in-memory CRIU for docker containersRanjan Sarpangala Venkatesh, Till Smejkal, Dejan S. Milojicic, Ada Gavrilovska. 53-65 [doi]
• DRAM errors in the field: a statistical approachDarko Zivanovic, Pouya Esmaili-Dokht, Sergi Moré, Javier Bartolome, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé. 69-84 [doi]
• Compression with multi-ECC: enhanced error resiliency for magnetic memoriesIrina Alam, Saptadeep Pal, Puneet Gupta. 85-100 [doi]
• Endurance enhancement of write-optimized STT-RAM cachesPuneet Saraf, Madhu Mutyam. 101-113 [doi]
• Transitioning scientific applications to using non-volatile memory for resilienceBrandon Nesterenko, Xiao Liu, Qing Yi, Jishen Zhao, Jiange Zhang. 114-125 [doi]
• Combining error statistics with failure prediction in memory page offliningXiaoming Du, Cong Li. 127-132 [doi]
• Fast validation of DRAM protocols with timed petri netsMatthias Jung 0001, Kira Kraft, Taha Soliman, Chirag Sudarshan, Christian Weis, Norbert Wehn. 133-147 [doi]
• M&MMs: navigating complex memory spaces with hwlocEdgar A. León, Brice Goglin, Andres Rubio Proaño. 149-155 [doi]
• Portable application guidance for complex memory systemsM. Ben Olson, Brandon Kammerdiener, Michael R. Jantz, Kshitij A. Doshi, Terry Jones. 156-166 [doi]
• Hopscotch: a micro-benchmark suite for memory performance evaluationAlif Ahmed, Kevin Skadron. 167-172 [doi]
• A unifying abstraction for data structure splicingLouis Ye, Mieszko Lis, Alexandra Fedorova. 173-183 [doi]
• Rethinking cycle accurate DRAM simulationShang Li, Rommel Sánchez Verdejo, Petar Radojkovic, Bruce Jacob. 184-191 [doi]
• STT-MRAM for real-time embedded systems: performance and WCET implicationsKazi Asifuzzaman, Mikel Fernández, Petar Radojkovic, Jaume Abella, Francisco J. Cazorla. 195-205 [doi]
• 3D photonics as enabling technology for deep 3D DRAM stackingSebastian Werner, Pouya Fotouhi, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis, Dilip P. Vasudevan. 206-221 [doi]
• Enabling scalable chiplet-based uniform memory architectures with silicon photonicsPouya Fotouhi, Sebastian Werner, Jason Lowe-Power, S. J. Ben Yoo. 222-334 [doi]
• Scaling the capacity of memory systems; evolution and key approachesKyriakos Paraskevas, Andrew Attwood, Mikel Luján, John Goodacre. 235-249 [doi]
• Data broker: a case for workflow enablement using a key/value approachLars Schneidenbach, Bruce D'Amora, Claudia Misale, Carlos H. A. Costa, Sara Kokkila Schumacher, Thomas Ward. 250-260 [doi]
• Towards a scatter-gather architecture: hardware and software issuesArun Rodrigues, Maya Gokhale, Gwendolyn Voskuilen. 261-271 [doi]
• Evaluation of intel 3D-xpoint NVDIMM technology for memory-intensive genomic workloadsDaniel Waddington, Mark Kunitomi, Clem Dickey, Samyukta Rao, Amir Abboud, Jantz Tran. 277-287 [doi]
• Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modulesOnkar Patil, Latchesar Ionkov, Jason Lee, Frank Mueller, Michael Lang 0003. 288-303 [doi]
• System evaluation of the Intel optane byte-addressable NVMIvy Bo Peng, Maya B. Gokhale, Eric W. Green. 304-315 [doi]
• SMART: STT-MRAM architecture for smart activation and sensingByoungchan Oh, Nilmini Abeyratne, Nam Sung Kim, Ronald G. Dreslinski, Trevor N. Mudge. 316-330 [doi]
• Simultaneously reducing cost and improving performance of NVM-based block devices via transparent data compressionXubin Chen, Yin Li, Jingpeng Hao, Hyunsuk Shin, Michael Suh, Tong Zhang 0002. 331-341 [doi]
• Design for ReRAM-based main-memory architecturesMeenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Shang Li, Mehdi Asnaashari, Sylvain Dubois, Donald Yeung, Bruce Jacob. 342-350 [doi]
• Faster slab reassignment in memcachedDaniel Byrne, Nilufer Onder, Zhenlin Wang. 353-362 [doi]
• LLAMA - automatic memory allocations: an LLVM pass and library for automatically determining memory allocationsDerrick Greenspan. 363-372 [doi]
• FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAMMuhammad M. Rafique, Zhichun Zhu. 373-382 [doi]
• Evaluating the effectiveness of program data features for guiding memory managementT. Chad Effler, Brandon Kammerdiener, Michael R. Jantz, Saikat Sengupta, Prasad A. Kulkarni, Kshitij A. Doshi, Terry Jones. 383-395 [doi]
• CASH: compiler assisted hardware design for improving DRAM energy efficiency in CNN inferenceAnup Sarma, Huaipan Jiang, Ashutosh Pattnaik, Jagadish Kotra, Mahmut Taylan Kandemir, Chita R. Das. 396-407 [doi]
• Statistical caching for near memory managementDong Chen, Fangzhou Liu, MingYang Jiao, Chen Ding, Sreepathi Pai. 411-416 [doi]
• Page migration support for disaggregated non-volatile memoriesVamsee Reddy Kommareddy, Simon David Hammond, Clayton Hughes, Ahmad Samih, Amro Awad. 417-427 [doi]
• The impact of cache inclusion policies on cache management techniquesLuna Backes, Daniel A. Jiménez. 428-438 [doi]
• ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processorsDhruv Gajaria, Tosiron Adegbija. 439-450 [doi]
• RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanismXiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang. 451-458 [doi]
• Predicting memory accesses: the road to compact ML-driven prefetcherAjitesh Srivastava, Angelos Lazaris, Benjamin Brooks, Rajgopal Kannan, Viktor K. Prasanna. 461-470 [doi]
• Inference engine benchmarking across technological platforms from CMOS to RRAMXiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu. 471-479 [doi]
• Machine learning based design space exploration for hybrid main-memory designSatyabrata Sen, Neena Imam. 480-489 [doi]
• CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip trainingHongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu. 490-496 [doi]
• Memory system characterization of deep learning workloadsZeshan Chishti, Berkin Akin. 497-505 [doi]
• Co-ML: a case for <u>co</u>llaborative <u>ML</u> acceleration using near-data processingShaizeen Aga, Nuwan Jayasena, Mike Ignatowski. 506-517 [doi]
• Statistical DRAM modelingShang Li, Bruce Jacob. 521-530 [doi]
• Demonstration of superconducting memory with passive transmission line-based readsRandy Posey, Randall Burnett, Quentin Herr, Donald Miller. 531-533 [doi]