Abstract is missing.
- A whole new ballgame - supercomputing on two AA batteries (keynote session)David Baker. 3 [doi]
- Eager writeback - a technique for improving bandwidth utilizationHsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens. 11-21 [doi]
- Silent stores for freeKevin M. Lepak, Mikko H. Lipasti. 22-31 [doi]
- A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data localityZhao Zhang, Zhichun Zhu, Xiaodong Zhang. 32-41 [doi]
- Predictor-directed stream buffersTimothy Sherwood, Suleyman Sair, Brad Calder. 42-53 [doi]
- On pipelining dynamic instruction scheduling logicJared Stark, Mary D. Brown, Yale N. Patt. 57-66 [doi]
- The impact of delay on the design of branch predictorsDaniel A. Jiménez, Stephen W. Keckler, Calvin Lin. 67-76 [doi]
- Improving BTB performance in the presence of DLLsStevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson. 77-86 [doi]
- Efficient checker processor designSaugata Chatterjee, Christopher T. Weaver, Todd M. Austin. 87-97 [doi]
- An integrated approach to accelerate data and predicate computations in hyperblocksAlexandre E. Eichenberger, Waleed Meleis, Suman Maradani. 101-111 [doi]
- Accurate and efficient predicate analysis with binary decision diagramsJohn W. Sias, Wen-mei W. Hwu, David I. August. 112-123 [doi]
- Modulo scheduling for a fully-distributed clustered VLIW architectureF. Jesús Sánchez, Antonio González. 124-133 [doi]
- Two-level hierarchical register file organization for VLIW processorsJavier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero. 137-146 [doi]
- PipeRench implementation of the instruction path coprocessorYuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen. 147-158 [doi]
- Efficient conditional operations for data-parallel architecturesUjval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany. 159-170 [doi]
- Flexible hardware acceleration for multimedia oriented microprocessorsFrederik Vermeulen, Lode Nachtergaele, Francky Catthoor, Diederik Verkest, Hugo De Man. 171-177 [doi]
- Very low power pipelines using significance compressionRamon Canal, Antonio González, James E. Smith. 181-190 [doi]
- A static power model for architectsJ. Adam Butts, Gurindar S. Sohi. 191-201 [doi]
- A framework for dynamic energy efficiency and temperature managementMichael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas. 202-213 [doi]
- Dynamic zero compression for cache energy reductionLuis Villa, Michael Zhang, Krste Asanovic. 214-220 [doi]
- Register integration: a simple and efficient implementation of squash reuseAmir Roth, Gurindar S. Sohi. 223-234 [doi]
- The store-load address table and speculative register promotionMatt Postiff, David Greene, Trevor N. Mudge. 235-244 [doi]
- Memory hierarchy reconfiguration for energy and performance in general-purpose processor architecturesRajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas. 245-257 [doi]
- Frequent value compression in data cachesJun Yang, Youtao Zhang, Rajiv Gupta. 258-265 [doi]
- Relational profiling: enabling thread-level parallelism in virtual machinesTimothy H. Heil, James E. Smith. 281-290 [doi]
- Calpa: a tool for automating selective dynamic compilationMarkus Mock, Craig Chambers, Susan J. Eggers. 291-302 [doi]
- Increasing the size of atomic instruction blocks using control flow assertionsSanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum. 303-313 [doi]
- Reducing wire delay penalty through value predictionJoan-Manuel Parcerisa, Antonio González. 317-326 [doi]
- Compiler controlled value prediction using branch predictor based confidenceEric Larson, Todd M. Austin. 327-336 [doi]
- Performance improvement with circuit-level speculationTong Liu, Shih-Lien Lu. 348-355 [doi]