Table of Contents

• Efficient and Effective Neural Networks for Automatic Test Pattern GenerationLizi Zhang, Azadeh Davoodi. 1 [doi]
• Learning to Compare Hardware Designs for High-Level SynthesisYunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li 0002, Ding Wang, Haoxing Ren, Yizhou Sun, Jason Cong. 2 [doi]
• FACT: Fast and Accurate Multi-Corner Predictor for Timing Closure in Commercial EDA FlowsJiajie Xu, Ziyue Han, Leilei Jin, Shiyang Wu, Hao Yan 0002, Longxing Shi. 3 [doi]
• ICDaIR: Distribution-aware Static IR Drop Prediction Flow Based on Image ClassificationPinquan Li, Yunfan Zuo, Yuwei Sun, Hao Yan 0002, Longxing Shi. 4 [doi]
• Enhancing the Capabilities of Quantum Transport Simulations Utilizing Machine Learning StrategiesAteeb Naseer, Yawar Hayat Zarkob, Musaib Rafiq, Mohammad Sajid Nazir, Owais Ahmad, Amit Agarwal, Somnath Bhowmick, Yogesh Singh Chauhan. 5 [doi]
• An ML-aided Approach to Automatically Generate Schematic Symbols in PCB EDA ToolsShiyu Gao, Keni Qiu. 6 [doi]
• IR-Aware ECO Timing Optimization Using Reinforcement LearningWenjing Jiang, Vidya A. Chhabria, Sachin S. Sapatnekar. 7 [doi]
• ReLS: Retrieval Is Efficient Knowledge Transfer For Logic SynthesisRongjian Liang, Chia-Tung Ho, Anthony Agnesina, Wen-Hao Liu 0001, Haoxing Ren. 8 [doi]
• A Parallel Simulation Framework Incorporating Machine Learning-Based Hotspot Detection for Accelerated Power Grid AnalysisYangfan Jiang, Jianfei Song, Xunzhao Yin, Xiao Dong, Songyu Sun, Yibo Lin, Zhou Jin 0001, Xiaoyu Yang, Cheng Zhuo. 9 [doi]
• PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLsChristopher Batten, Nathaniel Ross Pinckney, Mingjie Liu, Haoxing Ren, Brucek Khailany. 10 [doi]
• Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power OptimizationCristhian Roman-Vicharra, Yiran Chen 0001, Jiang Hu. 11 [doi]
• Parallel Per-tile Activation with Linear Superposition of Thermal Response for Solving Arbitrary Power Pattern in 3DIC Thermal SimulationHaiyang He, Norman Chang, Akhilesh Kumar, Jie Yang 0023, Wenbo Xia, Lang Lin, Jessica Yen, Haoliang Jiang, Rishikesh Ranade. 12 [doi]
• Automated Physical Design Watermarking Leveraging Graph Neural NetworksRuisi Zhang, Rachel Selina Rajarathnam, David Z. Pan, Farinaz Koushanfar. 13 [doi]
• Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level SynthesisZongyue Qin, Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, Jason Cong. 14 [doi]
• Automated C/C++ Program Repair for High-Level Synthesis via Large Language ModelsKangwei Xu, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann, Bing Li 0005. 15 [doi]
• High-Dimensional Yield Analysis Using Sparse Representation for Long-Tailed DistributionZiqi Wang, Weihan Sun, Zhongxi Guo, Xiao Shi, Longxing Shi. 16 [doi]
• An Efficient ML-based Hardware Trojan Localization Framework for RTL Security AnalysisRuchao Fan, Yongming Tang, Hao Sun, Jiyuan Liu 0006, He Li 0008. 17 [doi]
• AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL DesignRuidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li 0005. 18 [doi]
• TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical PathDonggyu Kim, Minjae Kim, Junseok Hur, Jakang Lee, Jinoh Cho, Seokhyeong Kang. 19 [doi]
• Efficient Subgraph Matching Framework for Fast Subcircuit IdentificationBoHao Li, Shizhang Wang, Tinghuan Chen, Qi Sun 0002, Cheng Zhuo. 20 [doi]
• TrojanForge: Generating Adversarial Hardware Trojan Examples Using Reinforcement LearningAmin Sarihi, Peter Jamieson, Ahmad Patooghy, Abdel-Hameed A. Badawy. 21 [doi]
• OpenROAD-Assistant: An Open-Source Large Language Model for Physical Design TasksUtsav Sharma, Bing-Yue Wu, Sai Rahul Dhanvi Kankipati, Vidya A. Chhabria, Austin Rovinski. 22 [doi]
• HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and BeyondStefan Abi-Karam, Rishov Sarkar, Allison Seigler, Sean Lowe, Zhigang Wei, Hanqiu Chen, Nanditha Rao, Lizy Kurian John, Aman Arora, Cong Hao. 23 [doi]
• MinBLoG: Minimization of Boolean Logic Functions using Graph Attention NetworkPrianka Sengupta, Aakash Tyagi, Jiang Hu, Vivek K. Rajan, Hesham Mostafa, Somdeb Majumdar. 24 [doi]
• Thermal Map Dataset for Commercial Multi/Many Core CPU/GPU/TPUJincong Lu, Sheldon X.-D. Tan. 25 [doi]
• Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip DesignAndre Nakkab, Sai Qian Zhang, Ramesh Karri, Siddharth Garg. 26 [doi]
• Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active LearningTao Bai, Zeyuan Deng, Peng Cao. 27 [doi]
• Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and SummarizationPrashanth Vijayaraghavan, Apoorva Nitsure, Charles Mackin, Luyao Shi, Stefano Ambrogio, Arvind Haran, Viresh Paruthi, Ali El-Zein, Dan Coops, David Beymer, Tyler Baldwin, Ehsan Degan. 28 [doi]
• LASP: LLM Assisted Security Property Generation for SoC VerificationAvinash Ayalasomayajula, Rui Guo, Jingbo Zhou, Sujan Kumar Saha, Farimah Farahmandi. 29 [doi]
• ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging EffectsXuanyi Tan, Peter Domanski, Sanmitra Banerjee, Krishnendu Chakrabarty. 30 [doi]
• Enabling Risk Management of Machine Learning Predictions for FPGA RoutabilityAndrew David Gunter, Maya Thomas, Nikhil Pratap Ghanathe, Steven J. E. Wilton. 31 [doi]
• Machine Learning VLSI CAD Experiments Should Consider Atomic Data GroupsAndrew David Gunter, Steven J. E. Wilton. 32 [doi]
• Human Language to Analog Layout Using GLayout Layout Automation FrameworkAli Hammoud, Chetanya Goyal, Sakib Pathen, Arlene Dai, Anhang Li, Gregory Kielian, Mehdi Saligane. 33 [doi]
• Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient DescentHaoyu Yang, Anthony Agnesina, Haoxing Ren. 34 [doi]
• LLM Based Physical Verification Runset GeneratorLuis Francisco, Srini Arikati. 35 [doi]
• When Device Modeling Meets Machine Learning: Opportunities and Challenges (Invited)Lining Zhang, Baokang Peng, Yu Li, Hengyi Liu, Wu Dai, Runsheng Wang. 36 [doi]
• Machine Learning for High Sigma Analog Designs (Invited)Srinivas Jallepalli. 37 [doi]
• LLM-Assisted Analytics in Semiconductor Test (Invited)Li-C. Wang. 38 [doi]
• (Invited) Redefining Outliers for On-Wafer Electrical TestingMichihiro Shintani, Takashi Sato 0001. 39 [doi]