Abstract is missing.
- Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable ProcessT. Kaya, Isao Shirakawa, Ryusuke Miyamoto, Takao Onoye.
- Challenges and Opportunities Created by the SoC ShockwaveM. Templeton.
- SoC s Trends and Challenges going to 0.10µmPhilippe Magarshack.
- Embedded Memory Test and RepairA. Kablanian.
- Soft Error Protection for Embedded MemoriesMichael Nicolaidis.
- Defect-Oriented Analysis of Memory BIST TestsAlvin Jee. 7-11 [doi]
- A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing TechniquesDavide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda. 12-16 [doi]
- A Scan-Bist Environment for Testing Embedded MemoriesFarzin Karimi, Fabrizio Lombardi. 17 [doi]
- Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash MemoriesDaniele Rossi, Cecilia Metra, Bruno Riccò. 27-31 [doi]
- High Speed 15 ns 4 Mbits SRAM for Space ApplicationBernard Coloma, Patrick Delaunay, Olivier Husson. 32-38 [doi]
- The YATE Fail-Safe Interface: The User s Point of ViewD. Bied-Charreton, D. Guillon, B. Jacques. 39-43 [doi]
- Fault Tolerant Insertion and Verification: A Case StudyAlberto Manzone, Diego De Costantini. 44-48 [doi]
- Design and Implementation of a Self-Checking Scheme for Railway Trackside SystemsLuca Schiano, Cecilia Metra, Diego Marino. 49-56 [doi]
- A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy ScenariosEmmanuel Rondey, Yann Tellier, Simone Borri. 57-61 [doi]
- A March-Based Fault Location Algorithm for Static Random Access MemoriesValery A. Vardanian, Yervant Zorian. 62-67 [doi]
- A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded MemoriesRei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu. 68 [doi]
- Design and Test of a 9-port SRAM for a 100Gb/s STS-1 SwitchRobert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu. 83 [doi]
- Adder Merged DRAM ArchitectureMasashi Hashimoto. 88-94 [doi]
- March SS: A Test for All Static Simple RAM FaultsSaid Hamdioui, A. J. van de Goor, Mike Rodgers. 95-100 [doi]
- Random Testing of Multi-Port Static Random Access MemoriesFarzin Karimi, Fred J. Meyer, Fabrizio Lombardi. 101-108 [doi]
- A Fault Modeling Technique to Test Memory BIST AlgorithmsRaja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla. 109-116 [doi]
- Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAMMichael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, Sue Ann Ung. 117-122 [doi]
- An Investigation into Crosstalk Noise in DRAM StructuresMichael Redeker, Bruce F. Cockburn, Duncan G. Elliott. 123 [doi]
- An Automated Design Methodology for EEPROM Cell (ADE)Jean Michel Portal, L. Forli, Hassen Aziza, Didier Née. 137-142 [doi]
- A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS TechnologyCyrille Dray, Philippe Gendrier. 143-148 [doi]
- A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile MemoriesCaroline Papaix, Jean Michel Daga. 149-156 [doi]
- Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC)T. Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond. 157-162 [doi]
- Converting an Embedded Low-Power SRAM from Bulk to PD-SOIMario R. Casu, Philippe Flatresse. 163-167 [doi]
- Decreasing EEPROM Programming Bias With Negative Voltage, Reliability ImpactR. Laffont, J. Razafindramora, P. Canet, Rachid Bouchakour, J. M. Mirabel. 168-176 [doi]
- Panel on Advanced Embedded Memory TechnologiesBruce F. Cockburn. 177-178 [doi]