Abstract is missing.
- Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based ModelingVyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra. 3-8 [doi]
- Fast Cycle-Accurate Interpreted SimulationZdenek Prikryl, Karel Masarik, Tomas Hruska, Adam Husar. 9-14 [doi]
- The importance of full target environment simulation tests for architecture validationJack L. Mason. 15-18 [doi]
- A Methodology for Power-aware Pipelining via High-Level Performance Model EvaluationsLuis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha. 19-24 [doi]
- Mutation Operators for Concurrent SystemC DesignsAlper Sen. 27-31 [doi]
- On the Mutation Analysis of SystemC TLM-2.0 StandardNicola Bombieri, Franco Fummi, Graziano Pravadelli. 32-37 [doi]
- Switch-Level Test Calculation for CMOS CircuitsJózsef Sziray. 41-48 [doi]
- A Path-Oriented Timing-Aware Diagnosis Methodology of At-Speed Transition TestsJing Zeng, Jing Wang, Michael Mateja. 49-54 [doi]
- An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault CoverageShadi Moazzeni, Saadat Poormozaffari, Amin Emami. 55-60 [doi]
- Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded PlatformFranco Fummi, Davide Quaglia, Sara Vinco, Giovanni Perbellini, Saul Saggin. 63-68 [doi]
- An ILP-Based Diagnosis Framework for Multiple Open-Segment DefectsChen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen. 69-72 [doi]
- Verification of the CoreNet Fabric with SystemVerilogRobert C. Page, Sakar Jain. 73-78 [doi]
- Test Generation for Precise Interrupts on Out-of-Order MicroprocessorsPadmaraj Singh, David L. Landis, Vijaykrishnan Narayanan. 79-82 [doi]
- System-level Performance Verification of Multicore Systems-on-ChipJim Holt, Jaideep Dastidar, David Lindberg, John Pape, Peng Yang. 83-87 [doi]
- A Reconfigurable Five-Stage Pipelined SAT SolverMona Safar, M. Watheq El-Kharashi, Mohamed Shalan, Ashraf Salem. 95-100 [doi]
- Induction-Based Formal Verification of SystemC TLM DesignsDaniel Große, Hoang M. Le, Rolf Drechsler. 101-106 [doi]
- Constraint Management and Checking in Template-Based Circuit DesignsRichard Bartolotti, Tom Burd, Brian McMinn, Arun Chandra. 107-113 [doi]