Abstract is missing.
- Ambipolar circuits for analog, mixed-signal, and radio-frequency applicationsKartik Mohanram, Xuebei Yang, Masoud Rostami, Guanxiong Liu, Alexander A. Balandin. 1-6 [doi]
- Ambipolar double gate CNTFETs based reconfigurable logic cellsKotb Jabeur, Ian O'Connor, Sébastien Le Beux, David Navarro. 7-13 [doi]
- Low-power design technique with ambipolar double gate devicesKotb Jabeur, Ian O'Connor, David Navarro, Sébastien Le Beux. 14-21 [doi]
- Gate-level modeling for CMOS circuit simulation with ultimate FinFETsNicolas Chevillon, Morgan Madec, Christophe Lallement. 22-29 [doi]
- Design exploration of ultra-low power non-volatile memory based on topological insulatorYuhao Wang, Hao Yu. 30-35 [doi]
- A conventional design for CLB implementation of a FPGA in quantum-dot cellular automata (QCA)Moein Kianpour, Reza Sabbaghi-Nadooshan. 36-42 [doi]
- Introducing OVP awareness to achieve an efficient permanent defect locatingTanvir Ahmed, Jun Yao, Yasuhiko Nakashima. 43-49 [doi]
- Irreversibility induced density limits and logical reversiblity in nanocircuitsIsmo Hänninen, Jarmo Takala. 50-54 [doi]
- Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistorsShashikanth Bobba, Pierre-Emmanuel Gaillardon, Jian Zhang, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli. 55-60 [doi]
- Ambipolar independent double gate FET logicIan O'Connor, Kotb Jabeur, Sébastien Le Beux, David Navarro. 61-68 [doi]
- Ternary volatile random access memory based on heterogeneous graphene-CMOS fabricSantosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz. 69-76 [doi]
- Macromodeling a phase change memory (PCM) cell by HSPICEPilin Junsangsri, Fabrizio Lombardi, Jie Han. 77-84 [doi]
- Crossbar architecture based on 2R complementary resistive switching memory cellWeisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller. 85-92 [doi]
- A Monte Carlo analysis of a write method used in passive nanoelectronic crossbarsArne Heittmann, Tobias G. Noll. 93-100 [doi]
- RRAM-based FPGA for "normally off, instantly on" applicationsOgun Turkyilmaz, Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Hraziia, Costin Anghel, Jean Michel Portal, Marc Bocquet. 101-108 [doi]
- Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devicesYao Wang 0002, Sorin Dan Cotofana, Liang Fang. 109-115 [doi]
- A Markovian, variation-aware circuit-level aging modelNicoleta Cucu Laurenciu, Sorin Dan Cotofana. 116-122 [doi]
- Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuitsSaleh Safiruddin, Mihai Lefter, Demid Borodin, George Razvan Voicu, Sorin Dan Cotofana. 123-130 [doi]
- Design and reliability analysis of multiple valued logic gates using carbon nanotube FETsJinghang Liang, Jie Han, Linbin Chen, Fabrizio Lombardi. 131-138 [doi]
- Emitter-coupled spin-transistor logicJoseph S. Friedman, Yehea I. Ismail, Gokhan Memik, Alan V. Sahakian, Bruce W. Wessels. 139-145 [doi]
- Room temperature double gate single electron transistor based standard cell libraryMohamed Amine-Bounouar, Arnaud Beaumont, Khalil El Hajjam, Francis Calmon, Dominique Drouin. 146-151 [doi]
- Cell design and comparative evaluation of a novel 1T memristor-based memoryVikas Sakode, Fabrizio Lombardi, Jie Han. 152-159 [doi]
- ToPoliNano: nanoarchitectures design made realStefano Frache, Diego Chiabrando, Mariagrazia Graziano, Fabrizio Riente, Giovanna Turvani, Maurizio Zamboni. 160-167 [doi]
- A novel write-scheme for data integrity in memristor-based crossbar memoriesAngelo Giuseppe Ruotolo, Marco Ottavi, Salvatore Pontarelli, Fabrizio Lombardi. 168-173 [doi]
- Stigmergic search with single electron tunneling technology based memory enhanced hubsSaleh Safiruddin, Sorin Cotofana, Ferdinand Peper. 174-180 [doi]
- Synthesis of topological quantum circuitsAlexandru Paler, Simon J. Devitt, Kae Nemoto, Ilia Polian. 181-187 [doi]
- Spintronic threshold logic array (STLA) - a compact, low leakage, non-volatile gate array architectureNishant Nukala, Niranjan Kulkarni, Sarma B. K. Vrudhula. 188-195 [doi]
- Spin wave nanofabric updateJ. G. Alzate, Parag Upadhyaya, M. Lewis, J. Nath, Y. T. Lin, K. Wong, S. Cherepov, P. Khalili Amiri, K. L. Wang, J. Hockel, A. Bur, G. P. Carman, S. Bender, Y. Tserkovnyak, J. Zhu, Y. J. Chen, I. N. Krivorotov, J. Katine, J. Langer, Prasad Shabadi, Santosh Khasanvis, Sankara Narayanan Rajapandian, Csaba Andras Moritz, A. Khitun. 196-202 [doi]
- Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approachesDamien Querlioz, Weisheng Zhao, Philippe Dollfus, Jacques-Olivier Klein, Olivier Bichler, Christian Gamrat. 203-210 [doi]
- Ultra low energy analog image processing using spin based neuronsMrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy. 211-217 [doi]
- RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layerMichael Soltiz, Cory E. Merkel, Dhireesha Kudithipudi, Garrett S. Rose. 218-225 [doi]
- Memristor-based reservoir computingManjari S. Kulkarni, Christof Teuscher. 226-232 [doi]