Abstract is missing.
- Learning Translation Invariant Recognition in Massively Parallel NetworksGeoffrey E. Hinton. 1-13
- Trace Theory and Systolic ComputationsMartin Rem. 14-33
- Boltzmann Machines and their ApplicationsEmile H. L. Aarts, Jan H. M. Korst. 34-50
- COBWEB-2: Structured Specification of a Wafer-Scale SupercomputerPaul Anderson, Chris Hankin, Paul H. J. Kelly, Peter Osmon, Malcolm J. Shute. 51-67
- A Novel Deadlock Free and Starvation Free Packet Switching Communication ProcessorJ. K. Annot, R. A. H. van Twist. 68-85
- A Parallel Architecture for Signal Understanding through Inference on Uncertain DataPier Giorgio Bosco, Egidio P. Giachin, G. Giandonato, G. Martinengo, Claudio Rullent. 86-102
- An Axiomatic Approach to the Specification of Distributed Computer ArchitecturesWerner Damm, Gert Döhmen. 103-120
- Computing on a Systolic Screen: Hulls, Contours and ApplicationsFrank K. H. A. Dehne, Jörg-Rüdiger Sack, Nicola Santoro. 121-133
- Multiprocessor Systems Programming in a High-Level Data-Flow LanguageJean-Luc Gaudiot, Liang-Teh Lee. 134-151
- The Twisted CubePeter A. J. Hilbers, Marion R. J. Koopman, Jan L. A. van de Snepscheut. 152-159
- An Implemented Method for Incremmental Systolic DesignChua-Huang Huang, Christian Lengauer. 160-177
- The Use of Parallel Functions in System DesignJ. K. Iliffe. 178-194
- The Translation of Processes into CircuitsAnne Kaldewaij. 195-212
- Mapping Strategies in Message Based Multiprocessor SystemsOttmar Krämer, Heinz Mühlenbein. 213-225
- Hardware Memory Management for Large Knowledge BasesSimon H. Lavington, M. Standing, Y. J. Jiang, C.-J. Wang, M. E. Waite. 226-241
- Transputer-Based Experiments with the ZAPP ArchitectureD. L. McBurney, M. Ronan Sleep. 242-259
- Synthesis of Systolic arrays for Inductive ProblemsCatherine Mongenet, Guy-René Perrin. 260-277
- Practical Parallelism using Transputer ArraysDavid J. Pritchard, C. R. Askew, D. B. Carpenter, Ian Glendinning, Anthony J. G. Hey, Denis A. Nicole. 278-294
- Systolic Array Synthesis by Static Analysis of Program DependenciesSanjay V. Rajopadhye, Richard Fujimoto. 295-310
- Specification of a Pipelined Event Driven Simulator using FP2Peter Schäfer, Ph. Schnoebelen. 311-328
- A Layered Emulator for Design Evaluation of MIMD Multiprocessors with Shared MemoryPer Stenström, Lars Philipson. 329-344
- The Alliant FX/Series: A Language Driven Architecture for Parallel Processing of Dusty Deck FortranJack A. Test, Mat Myszewski, Richard C. Swift. 345-356
- Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)Peter H. Welch. 357-373
- A Two-Level Approach to Logic plus Functional Programming IntegrationMarco Bellia, Pier Giorgio Bosco, Elio Giovannetti, Giorgio Levi, Corrado Moiso, Catuscia Palamidessi. 374-393
- Overview of a Parallel Reduction Machine ProjectD. I. Bevan, Geoffrey L. Burn, R. J. Karia. 394-413
- An Overview of DDC: Delta Driven ComputerRubén González-Rubio, J. Rohmer, A. Bradier. 414-433
- Design and Implementaion of a Parallel Inference Machine for First Order Logic: An OverviewPhilippe Jorrand. 434-445
- Multi-Level Simulator for VLSI - An OverviewP. Mehring, E. Aposporidis. 446-460
- The DOOM System and its Applications: A Survey of Esprit 415 Subproject A, Philips Research LaboratriesEddy Odijk. 461-479