Abstract is missing.
- Constraints, Hurdles, and Opportunities for a Successful European Take-Up ActionRene van Leuken, Reinder Nouta, Alexander de Graaf. 1-2 [doi]
- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation TechniquesManuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon. 3-13 [doi]
- Power Models for Semi-autonomous RTL MacrosAlessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino. 14-23 [doi]
- Power Macro-Modelling for Firm-MacroGerd Jochens, Lars Kruse, Eike Schmidt, Ansgar Stammermann, Wolfgang Nebel. 24-35 [doi]
- RTL Estimation of Steering Logic PowerCrina Anton, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino, Alessandro Bogliolo. 36-46 [doi]
- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital ReceiversNikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis. 47-55 [doi]
- Framework for High-Level Power Estimation of Signal Processing ArchitecturesAchim Freimann. 56-65 [doi]
- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System BusesClaudia Kretzschmar, Robert Siegmund, Dietmar Müller. 66-75 [doi]
- Accurate Power Estimation of Logic Structures Based on Timed Boolean FunctionsGeorge Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis. 76-87 [doi]
- A Holistic Approach to System Level Energy OptimizationMary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam. 88-107 [doi]
- Early Power Estimation for System-on-Chip DesignsMarcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante. 108-117 [doi]
- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array ArchitecturesReiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger. 118-128 [doi]
- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS DesignPhilippe Maurine, Mustapha Rezzoug, Daniel Auvergne. 129-138 [doi]
- Impact of Voltage Scaling on Glitch Power ConsumptionHenrik Eriksson, Per Larsson-Edefors. 139-148 [doi]
- Degradation Delay Model Extension to CMOS GatesJorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia. 149-158 [doi]
- Second Generation Delay Model for Submicron CMOS ProcessMustapha Rezzoug, Philippe Maurine, Daniel Auvergne. 159-167 [doi]
- Semi-modular Latch Chains for Asynchronous Circuit DesignNikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev. 168-177 [doi]
- Asynchronous First-in First-out QueuesFrancesco Pessolano, Joep L. W. Kessels. 178-186 [doi]
- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and PerformanceAthanasios Kakarountas, K. Papadomanolakis, V. Kokkinos, Constantinos E. Goutis. 187-194 [doi]
- VLSI Implementation of a Low-Power High-Speed Self-Timed AdderPasquale Corsonello, Stefania Perri, Giuseppe Cocorullo. 195-204 [doi]
- Low Power Design Techniques for Contactless ChipcardsHolger Sedlak. 205-206 [doi]
- Dynamic Memory Design for Low Data-Retention PowerJoohee Kim, Marios C. Papaefthymiou. 207-216 [doi]
- Double-Latch Clocking Scheme for Low-Power I.P. CoresClaude Arm, Jean-Marc Masgonty, Christian Piguet. 217-224 [doi]
- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor ChipSantanu Dutta. 225-232 [doi]
- Cost-Efficient C-Level Design of an MPEG-4 Video DecoderKristof Denolf, Peter Vos, Jan Bormans, Ivo Bolsens. 233-242 [doi]
- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia ApplicationsDimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis. 243-254 [doi]
- Design of Reversible Logic Circuits by Means of Control GatesAlexis De Vos, Bart Desoete, A. Adamski, Piotr Pietrzak, M. Sibínski, T. Widerski. 255-264 [doi]
- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional GatesMassimo Alioto, Gaetano Palumbo. 265-275 [doi]
- An Adiabatic MultiplierChristoph Saas, A. Schlaffer, Josef A. Nossek. 276-284 [doi]
- Logarithmic Number System for Low-Power ArithmeticVassilis Paliouras, Thanos Stouraitis. 285-294 [doi]
- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital CircuitsRaúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda. 295-305 [doi]
- PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-CircuitsAndreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel. 306-315 [doi]
- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI CircuitsAntonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia. 316-326 [doi]
- Computer Aided Generation of Analytic Models for Nonlinear Function BlocksTom Wichmann, Manfred Thole. 327-335 [doi]