Table of Contents

• A Power-Efficient and Scalable Load-Store Queue DesignFernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Michael C. Huang, Francisco Tirado. 1-9 [doi]
• Power Consumption Reduction Using Dynamic Control of Micro Processor PerformanceDavid Rios-Arambula, Aurélien Buhrig, Marc Renaudin. 10-18 [doi]
• Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature ApplicationsPhilippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat. 19-29 [doi]
• Dynamic Instruction Cascading on GALS MicroprocessorsHiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura. 30-39 [doi]
• Power Reduction of Superscalar Processor Functional Units by Resizing Adder-WidthGuadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar. 40-48 [doi]
• A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri NetMeuse N. Oliveira Jr., Paulo Romero Martins Maciel, Ricardo Massa Ferreira Lima, Angelo Ribeiro, Cesar Oliveira, Adilson Arcoverde, Raimundo S. Barreto, Eduardo Tavares, Leonardo Amorim. 49-58 [doi]
• Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip MemoryRodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis. 59-68 [doi]
• Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded SystemsJosé Manuel Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor, Francisco Tirado, Jose Manuel Mendias. 69-78 [doi]
• Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time ApplicationsHuizhan Yi, Xuejun Yang. 79-88 [doi]
• Systematic Preprocessing of Data Dependent Constructs for Embedded SystemsMartin Palkovic, Erik Brockmeyer, Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor. 89-98 [doi]
• Temperature Aware Datapath SchedulingAli Manzak. 99-106 [doi]
• Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet TransformBert Geelen, Gauthier Lafruit, V. Ferentinos, Rudy Lauwereins, Diederik Verkest. 107-116 [doi]
• Improving the Memory Bandwidth Utilization Using Loop TransformationsMinas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. 117-126 [doi]
• Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled ArchitecturesAmjad Mohsen, Richard Hofmann. 127-136 [doi]
• Design of Digital Filters for Low Power Applications Using Integer Quadratic ProgrammingMustafa Aktan, Günhan Dündar. 137-145 [doi]
• A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of AbstractionArne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel. 146-155 [doi]
• An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network EnvironmentsHyun-Ho Kim, Jung Hee Kim, Yong-hyeog Kang, Young Ik Eom. 156-165 [doi]
• Energy-Aware System-on-Chip for 5 GHz Wireless LANsLabros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon. 166-176 [doi]
• Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR ReductionTheodoros Giannopoulos, Vassilis Paliouras. 177-186 [doi]
• An Activity Monitor for Power/Performance Tuning of CMOS Digital CircuitsJosep Rius, José Pineda de Gyvez, Maurice Meijer. 187-196 [doi]
• Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode TechniquesJean-Félix Perotto, Stefan Cserveny. 197-206 [doi]
• Power Consumption in Reversible Logic Addressed by a Ramp VoltageAlexis De Vos, Yvan Van Rentergem. 207-216 [doi]
• Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V::th:: Assignment and Path BalancingYuanlin Lu, Vishwani D. Agrawal. 217-226 [doi]
• Back Annotation in High Speed Asynchronous DesignPankaj Golani, Peter A. Beerel. 227-236 [doi]
• Optimization of Reliability and Power Consumption in Systems on a ChipTajana Simunic, Kresimir Mihic, Giovanni De Micheli. 237-246 [doi]
• Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCsMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. 247-256 [doi]
• A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC DesignYici Cai, Bin Liu, Qiang Zhou, Xianlong Hong. 257-266 [doi]
• Power Supply Selective Mapping for Accurate Timing AnalysisMariagrazia Graziano, Cristiano Forzan, Davide Pandini. 267-276 [doi]
• Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip BusesRoshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen. 277-285 [doi]
• PSK Signalling on NoC BusesCrescenzo D Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev. 286-296 [doi]
• Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus EncodingAshutosh Chakraborty, Enrico Macii, Massimo Poncino. 297-307 [doi]
• Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate SizingGiorgos Dimitrakopoulos, Dimitris Nikolos. 308-317 [doi]
• Efficient Simulation of Power/Ground Networks with Package and ViasJin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan. 318-328 [doi]
• Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance OptimisationGregorio Cappuccino, Andrea Pugliese 0002, Giuseppe Cocorullo. 329-336 [doi]
• Application of Internode Model to Global Power Consumption Estimation in SCMOS GatesAlejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Julian Viejo. 337-347 [doi]
• Compact Static Power Model of Complex CMOS GatesJosé Luis Rosselló, Sebastià A. Bota, Jaume Segura. 348-354 [doi]
• Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical ModelMassimo Alioto, Gaetano Palumbo, Massimo Poli. 355-363 [doi]
• Statistical Critical Path Analysis Considering CorrelationsYaping Zhan, Andrzej J. Strojwas, Mahesh Sharma, David Newmark. 364-373 [doi]
• A CAD Platform for Sensor Interfaces in Low-Power ApplicationsDidier Van Reeth, Georges G. E. Gielen. 374-381 [doi]
• An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy ConstraintsEduardo Tavares, Raimundo S. Barreto, Paulo Romero Martins Maciel, Meuse N. Oliveira Jr., Adilson Arcoverde, Gabriel Alves, Ricardo Massa Ferreira Lima, Leonardo Barros, Arthur Bessa. 382-392 [doi]
• Efficient Post-layout Power-Delay Curve GenerationMiodrag Vujkovic, David Wadkins, Carl Sechen. 393-403 [doi]
• Power - Performance Optimization for Custom Digital CircuitsRadu Zlatanovici, Borivoje Nikolic. 404-414 [doi]
• Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAsSiobhán Launders, Colin Doyle, Wesley Cooper. 415-424 [doi]
• Logic-Level Fast Current Simulation for Digital CMOS CircuitsPaulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa, Julian Viejo. 425-435 [doi]
• Design of Variable Input Delay Gates for Low Dynamic Power CircuitsTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell. 436-445 [doi]
• Two-Phase Clocking and a New Latch Design for Low-Power Portable ApplicationsFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner. 446-455 [doi]
• Power Dissipation Reduction During Synthesis of Two-Level Logic Based on Probability of Input Vectors ChangesIreneusz Brzozowski, Andrzej Kos. 456-465 [doi]
• Energy-Efficient Value-Based Selective Refresh for Embedded DRAMsKimish Patel, Luca Benini, Enrico Macii, Massimo Poncino. 466-476 [doi]
• Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMsPrassanna Sithambaram, Alberto Macii, Enrico Macii. 477-487 [doi]
• Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron TechnologyArmin Wellig, Julien Zory. 488-497 [doi]
• An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder BuffersShadi T. Khasawneh, Kanad Ghose. 498-507 [doi]
• Parameter Variation Effects on Timing Characteristics of High Performance Clocked RegistersWilliam R. Roberts, Dimitrios Velenis. 508-517 [doi]
• Low-Power Aspects of Nonlinear Signal ProcessingKonstantina Karagianni, Vassilis Paliouras. 518-527 [doi]
• Reducing Energy Consumption of Computer Display by Camera-Based User MonitoringVasily G. Moshnyaga, Eiji Morikawa. 528-539 [doi]
• Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set PerspectivesNabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault. 540-549 [doi]
• A Design Methodology for Secured ICs Using Dynamic Current Mode LogicFrançois Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat. 550-560 [doi]
• Power Consumption Characterisation of the Texas Instruments TMS320VC5510 DSPMiguel Casas-Sanchez, Jose Rizo-Morente, Chris J. Bleakley. 561-570 [doi]
• A Method to Design Compact Dual-rail Asynchronous PrimitivesAlin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine. 571-580 [doi]
• Enhanced GALS Techniques for Datapath ApplicationsEckhard Grass, Frank Winkler, Milos Krstic, Alexandra Julius, Christian Stahl, Maxim Piz. 581-590 [doi]
• Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling StudyHaralambos Michail, Athanasios Kakarountas, George N. Selimis, Costas E. Goutis. 591-600 [doi]
• Area-Aware Pipeline Gating for Embedded ProcessorsBabak Salamat, Amirali Baniasadi. 601-608 [doi]
• Fast Low-Power 64-Bit Modular Hybrid AdderStefania Perri, Pasquale Corsonello, Giuseppe Cocorullo. 609-617 [doi]
• Speed Indicators for Circuit OptimizationAlexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard. 618-628 [doi]
• Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary AlgorithmsFrancisco de Toro, Raúl Jiménez, Manuel Sánchez, Julio Ortega. 629-637 [doi]
• Power-Clock Gating in Adiabatic Logic CircuitsPhilip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel. 638-646 [doi]
• The Design of an Asynchronous Carry-Lookahead Adder Based on Data CharacteristicsYijun Liu, Stephen B. Furber. 647-656 [doi]
• Efficient Clock Distribution Scheme for VLSI RNS-Enabled ControllersDaniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz. 657-665 [doi]
• Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table ArchitecturesFrancisco-Javier Veredas, Jordi Carrabina. 666-673 [doi]
• The Optimal Wire Order for Low Power CMOSPaul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele. 674-683 [doi]
• Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure WaterBécharia Nadji. 684-692 [doi]
• Temperature Dependency in UDSM ProcessB. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine. 693-703 [doi]
• Circuit Design Techniques for On-Chip Power Supply Noise Monitoring SystemHoward Chen, Louis Hsu. 704-713 [doi]
• A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential TransconductorHamid Reza Sadr M. N. 714-723 [doi]
• A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency DividersMarko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija. 724-732 [doi]
• Digital Hearing Aids: Challenges and Solutions for Ultra Low PowerWolfgang Nebel, Bärbel Mertsching, Birger Kollmeier. 733 [doi]
• Tutorial Hearing Aid AlgorithmsThomas Rohdenburg, Volker Hohmann, Birger Kollmeier. 734 [doi]
• Optimization of Digital Audio Processing Algorithms Suitable for Hearing AidsArne Schulz, Wolfgang Nebel. 735-736 [doi]
• Optimization of Modules for Digital Audio ProcessingThomas Eisenbach, Bärbel Mertsching, Nikolaus Voß, Frank Schmidtmeier. 737-746 [doi]
• Traveling the Wild Frontier of Ultra Low-Power DesignJan M. Rabaey. 747 [doi]
• DLV (Deep Low Voltage): Circuits and DevicesSung-Bae Park. 748 [doi]
• Wireless Sensor Networks: A New Life ParadigmMagdy Bayoumi. 749 [doi]
• Cryptography: Circuits and Systems ApproachOdysseas G. Koufopavlou, George N. Selimis, Nicolas Sklavos, Paris Kitsos. 750 [doi]