Abstract is missing.
- Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential AlgorithmsAnatoly Prihozhy, Daniel Mlynek. 1-11 [doi]
- Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level ParallelismDaniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest. 12-23 [doi]
- Handheld System Energy Reduction by OS-Driven RefreshVasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak. 24-35 [doi]
- Delay Constrained Register Transfer Level Dynamic Power EstimationSriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri. 36-46 [doi]
- Circuit Design Style for Energy Efficiency: LSDL and Compound DominoXiao Yan-Yu, Robert K. Montoye, Kevin J. Nowka, Bart R. Zeydel, Vojin G. Oklobdzija. 47-55 [doi]
- Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction LeakageDomenik Helms, Marko Hoyer, Wolfgang Nebel. 56-65 [doi]
- Leakage Power Characterization Considering Process VariationsJosé Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura. 66-74 [doi]
- Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and PerformanceA. G. Silva-Filho, F. R. Cordeiro, Remy Eskinazi Sant Anna, Manoel Eusebio de Lima. 75-83 [doi]
- System Level Multi-bank Main Memory Configuration for Energy ReductionHanene Ben Fradj, Cécile Belleudy, Michel Auguin. 84-94 [doi]
- SRAM CP: A Charge Recycling Design Schema for SRAMKa-Ming Keung, Akhilesh Tyagi. 95-106 [doi]
- Compiler-Driven Leakage Energy Reduction in Banked Register FilesDavid Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo. 107-116 [doi]
- Impact of Array Data Flow Analysis on the Design of Energy-Efficient CircuitsM. Hillers, W. Nebel. 117-126 [doi]
- Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design LimitationsBart R. Zeydel, Vojin G. Oklobdzija. 127-136 [doi]
- Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage RegulatorStefan Cserveny. 137-147 [doi]
- Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit DesignMilena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija. 148-156 [doi]
- Power Modeling of a NoC Based Design for High Speed Telecommunication SystemsPhilippe Grosse, Yves Durand, Paul Feautrier. 157-168 [doi]
- Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire CapacitanceTudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner. 169-180 [doi]
- Estimation of Power Reduction by On-Chip Transmission Line for 45nm TechnologyKenichi Okada, Takumi Uezono, Kazuya Masu. 181-190 [doi]
- Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS ArchitecturesAbbas Sheibanyrad, Alain Greiner. 191-202 [doi]
- Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM TransmittersTheodoros Giannopoulos, Vassilis Paliouras. 203-213 [doi]
- Dynamic Management of Thermally-Induced Clock Skew: An Implementation PerspectiveAshutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino. 214-224 [doi]
- A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy OperationToshiro Akino, Takashi Hamahata. 225-236 [doi]
- Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) TechniqueB. Chung, J. B. Kuo. 237-246 [doi]
- Low Power Distance Measurement Unit for Real-Time Hardware Motion EstimatorsTiago Dias, Nuno Roma, Leonel Sousa. 247-255 [doi]
- Reducing Energy Dissipation of Wireless Sensor Processors Using Silent-Store-Filtering MoteCacheGurhan Kucuk, Can Basaran. 256-266 [doi]
- A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory BusReouven Elbaz, Lionel Torres, Gilles Sassatelli, Pierre Guillemin, Michel Bardouillet, Albert Martinez. 267-279 [doi]
- Methodology for Dynamic Power Verification of Contactless SmartcardsJulien Mercier, Christian Dufaza, Mathieu Lisart. 280-291 [doi]
- New Battery Status Checking Method for Implantable Biomedical ApplicationsJong-Pil Son, Kyu-Young Kim, Ji-Yong Jeong, Yogendera Kumar, Soo-Won Kim. 292-300 [doi]
- Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing AnalysisDaniel Lima Ferrão, Ricardo Reis, José Luís Almada Güntzel. 301-310 [doi]
- A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion TechniqueAndrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo. 311-318 [doi]
- Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design FlowChristophe Alexandre, Marek Sroka, Hugo Clément, Christian Masson. 319-328 [doi]
- Receiver Modeling for Static Functional Crosstalk AnalysisMini Nanua, David Blaauw. 329-339 [doi]
- Modeling of Crosstalk Fault in Defective InterconnectsAjoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier. 340-349 [doi]
- Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic CircuitsJi-Yong Jeong, Gil-Su Kim, Jong-Pil Son, Woo-Jin Rim, Soo-Won Kim. 350-359 [doi]
- Energy-Delay Space Analysis for Clocked Storage Elements Under Process VariationsChristophe Giacomotto, Nikola Nedovic, Vojin G. Oklobdzija. 360-369 [doi]
- IR-drop Reduction Through Combinational Circuit PartitioningHai Lin, Yu Wang, Rong Luo, Huazhong Yang, Hui Wang. 370-381 [doi]
- Low-Power Register File Based on Adiabatic Logic CircuitsJianping Hu, Hong Li, Yangbo Wu. 382-392 [doi]
- High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOIMasayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa. 393-402 [doi]
- Designing Alternative FPGA Implementations Using Spatial Data from Hardware ResourcesKostas Siozios, Dimitrios Soudris, Antonios Thanailakis. 403-414 [doi]
- An FPGA Power Aware Design FlowDavid Elléouet, Yannig Savary, Nathalie Julien. 415-424 [doi]
- The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical ProcessingYijun Liu, Steve Furber, Zhenkun Li. 425-438 [doi]
- Optimization of Master-Slave Flip-Flops for High-Performance ApplicationsRaúl Jiménez, Pilar Parra, Javier Castro, Manuel Sánchez, Antonio J. Acosta. 439-449 [doi]
- Hierarchical Modeling of a Fractional Phase Locked LoopBenjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod. 450-457 [doi]
- Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICsRégis Roubadia, Sami Ajram, Guy Cathébras. 458-467 [doi]
- Statistical Characterization of Library Timing PerformanceV. Migairou, Robin Wilson, S. Engels, Nadine Azémard, Philippe Maurine. 468-476 [doi]
- Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar MicroprocessorsOguz Ergin. 477-485 [doi]
- Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOSSaihua Lin, Hongli Gao, Huazhong Yang. 486-495 [doi]
- Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform VariationsJürgen Rauscher, Hans-Jörg Pfleiderer. 496-503 [doi]
- Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD ModelingSaihua Lin, Huazhong Yang. 504-513 [doi]
- A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance ProcessorsGuadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López. 514-523 [doi]
- Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time ApplicationsAndrea Pugliese 0002, Gregorio Cappuccino, Giuseppe Cocorullo. 524-531 [doi]
- Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware DesignDavide Pandini, Guido A. Repetto. 532-542 [doi]
- A Scalable Power Modeling Approach for Embedded Memory Using LIB FormatWen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu. 543-552 [doi]
- Improving Energy Efficiency Via Speculative Multithreading on MultiCore ProcessorsToshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu. 553-562 [doi]
- A CMOS Compatible Charge Recovery Logic Family for Low Supply VoltagesClemens Schlachta, Manfred Glesner. 563-572 [doi]
- A Framework for Estimating Peak Power in Gate-Level CircuitsDiganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta. 573-582 [doi]
- QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance AnalysisEslam Yahya, Marc Renaudin. 583-592 [doi]
- Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES AlgorithmMassimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli. 593-602 [doi]
- Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec CircuitryJosé Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis. 603-613 [doi]
- A Novel Methodology to Reduce Leakage Power in CMOS Complementary CircuitsPreetham Lakshmikanthan, Adrian Nunez. 614-623 [doi]
- Techniques to Enhance the Resistance of Precharged Busses to Differential Power AnalysisMassimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli. 624-633 [doi]
- Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA AttacksAlin Razafindraibe, Michel Robert, Philippe Maurine. 634-644 [doi]
- A Method for Switching Activity Analysis of VHDL-RTL Combinatorial CircuitsFelipe Machado, Teresa Riesgo, Yago Torroja. 645-657 [doi]
- Nanoelectronics: Challenges and OpportunitiesGiovanni De Micheli. 658 [doi]
- Static and Dynamic Power Reduction by Architecture SelectionChristian Piguet, Christian Schuster, Jean-Luc Nagel. 659-668 [doi]
- Asynchronous Design for High-Speed and Low-Power CircuitsPeter A. Beerel. 669 [doi]
- Design for Volume Manufacturing in the Deep Submicron ERARobin Wilson. 670 [doi]
- The Holy Grail of Holistic Low-Power DesignFrancesco Pessolano. 671 [doi]
- Top Verification of Low Power System with Checkerboard ApproachJean Oudinot. 672 [doi]
- The Power Forward InitiativeFrancois Thomas. 673 [doi]