Table of Contents

• openHMC - a configurable open-source hybrid memory cube controllerJuri Schmidt, Ulrich Brüning. 1-6 [doi]
• Improving FPGA NoC performance using virtual cut-through switching techniquePongstorn Maidee, Alireza Kaviani. 1-6 [doi]
• Side channel attack on multiprecision multiplier used in protected ECDSA implementationMichal Varchola, Milos Drutarovský, Marek Repka, Pavol Zajac. 1-6 [doi]
• An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databasesChristopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Sven Groppe. 1-7 [doi]
• Optimizing memory performance for FPGA implementation of pagerankShijie Zhou, Charalampos Chelmis, Viktor K. Prasanna. 1-6 [doi]
• G-DMA: improving memory access performance for hardware accelerated sparse graph computationAndrew Bean, Nachiket Kapre, Peter Y. K. Cheung. 1-6 [doi]
• Efficient and flexible NoC-based group communication for secure MPSoCsJohanna Sepúlveda, Daniel Flórez, Guy Gogniat. 1-6 [doi]
• Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architecturesSen Ma, Hongyuan Ding, Miaoqing Huang, David L. Andrews. 1-6 [doi]
• On how to efficiently accelerate brain network analysis on FPGA-based computing systemGiulia Gnemmi, Mattia Crippa, Gianluca Durelli, Riccardo Cattaneo, Gabriele Pallotta, Marco D. Santambrogio. 1-6 [doi]
• A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocolsBenjamin Buhrow, Karl E. Fritz, Barry K. Gilbert, Erik S. Daniel. 1-7 [doi]
• FPGA-based circular hough transform with graph clustering for vision-based multi-robot trackingArif Irwansyah, Omar W. Ibraheem, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001. 1-8 [doi]
• FPGA-based acceleration of high density myoelectric signal processingAlexander Boschmann, Andreas Agne, Linus Witschen, Georg Thombansen, Florian Kraus, Marco Platzner. 1-8 [doi]
• Partial reconfiguration and specialized circuitry for flexible FPGA-based packet processingSven Hager, Daniel Bendyk, Björn Scheuermann. 1-6 [doi]
• Adaptive controller using runtime partial hardware reconfiguration for unmanned aerial vehicles (UAVs)Nikhil Thomas, Andrew Felder, Christophe Bobda. 1-7 [doi]
• Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systemsHugo A. Andrade, Patricia Derler, John C. Eidson, Ya-Shian Li-Baboud, Aviral Shrivastava, Kevin Stanton, Marc Weiss. 1-6 [doi]
• A real-time reconfigurable architecture for face detectionViorel Suse, Dan Ionescu. 1-6 [doi]
• An efficient structure for run-time configuration of synthesis and channelizer filter banksThaddeus Koehn, Matthew Carrick, Peter Athanas. 1-6 [doi]
• A universal hardware API for authenticated ciphersEkawat Homsirikamol, William Diehl, Ahmed Ferozpuri, Farnoud Farahmand, Malik Umar Sharif, Kris Gaj. 1-8 [doi]
• Multiple contexts in a multi-ported VLIW register file implementationJoost Hoozemans, Jens Johansen, Jeroen van Straten, Anthony Brandon, Stephan Wong. 1-6 [doi]
• Power measurements and analysis for dynamic circuit specializationAmit Kulkarni, Robin Bonamy, Dirk Stroobandt. 1-6 [doi]
• Thoroughly analyzing the use of ring oscillators for on-chip hardware trojan detectionMaxime Lecomte, Jacques J. A. Fournier, Philippe Maurine. 1-6 [doi]
• Reconfigurable coprocessors synthesis in the MPEG-RVC domainCarlo Sau, Luca Fanni, Paolo Meloni, Luigi Raffo, Francesca Palumbo. 1-8 [doi]
• Exploration of polynomial multiplication algorithms for homomorphic encryption schemesVincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat. 1-6 [doi]
• High throughput sketch based online heavy change detection on FPGADa Tong, Viktor K. Prasanna. 1-8 [doi]
• Keynote 2 - Towards datacenter computing with FPGAsGordon Ghiu. 1 [doi]
• A resource-efficient multi-camera GigE vision IP core for embedded vision processing platformsOmar W. Ibraheem, Arif Irwansyah, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001. 1-6 [doi]
• Deeply hardware-entangled reconfigurable logic and interconnectBurak Erbagci, Mudit Bhargava, Rachel Dondero, Ken Mai. 1-8 [doi]
• UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAsVincent Mirian, Paul Chow. 1-6 [doi]
• Floating point CORDIC-based architecture for powering computationJoshua Mack, Sam Bellestri, Daniel Llamocca. 1-6 [doi]
• A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architecturesEnrico A. Deiana, Marco Rabozzi, Riccardo Cattaneo, Marco D. Santambrogio. 1-6 [doi]
• Private circuits II versus fault injection attacksHenitsoa Rakotomalala, Xuan Thuy Ngo, Zakaria Najm, Jean-Luc Danger, Sylvain Guilley. 1-9 [doi]
• Shape exploration for modules in rapid assembly workflowsKevin Lee, Peter Athanas. 1-7 [doi]
• FPGA-based visual control of robot manipulators using dynamic perceptibilityJ. Pérez, A. Alabdo, G. J. Garcia, J. Pomares, F. Torres. 1-7 [doi]
• Accelerating the construction of BRIEF descriptors using an FPGA-based architectureRoberto de Lima, José Martínez-Carranza, Alicia Morales-Reyes, René Cumplido. 1-6 [doi]
• A run-length encoding co-processor for retinal image texture analysisHamza Bendaoudi, Qifeng Gan, Farida Cheriet, Houssem Ben Tahar, J. M. Pierre Langlois. 1-6 [doi]
• Exploiting hardware abstraction for hybrid parallel computing frameworkHongyuan Ding, Miaoqing Huang. 1-7 [doi]
• Design and exploration of routing methods for NoC-based multicore systemsPoona Bahrebar, Dirk Stroobandt. 1-4 [doi]
• Exploring the energy consumption of lightweight blockciphers in FPGASubhadeep Banik, Andrey Bogdanov, Francesco Regazzoni. 1-6 [doi]
• Real-time pedestrian detection on a xilinx zynq using the HOG algorithmJens Rettkowski, Andrew Boutros, Diana Göhringer. 1-8 [doi]
• Using type transformations to generate program variants for FPGA design space explorationSyed Waqar Nabi, Wim Vanderbauwhede. 1-6 [doi]
• Designing customized ISA processors using high level synthesisSam Skalicky, Tejaswini Ananthanarayana, Sonia López, Marcin Lukowiak. 1-6 [doi]
• Analysis of FPGA and software approaches to simulate unconventional computer architecturesMohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján. 1-8 [doi]
• Exploiting the brownian bridge technique to improve longstaff-schwartz american option pricing on FPGA systemsJavier Alejandro Varela, Christian Brugger, Christian de Schryver, Norbert Wehn, Songyin Tang, Steffen Omland. 1-6 [doi]
• Scalable modular hardware platform for FPGA based industrial radar flowmetersTimo Jaeschke, Patrick Imberg, Michael Zapke, Michael Hübner, Nils Pohl. 1-6 [doi]
• Low latency solver for linear equation systems in floating point arithmeticJean-Pierre David. 1-7 [doi]
• Power modelling for saving strategies in coarse grained reconfigurable systemsTiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo. 1-4 [doi]
• FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networksArmando Astarloa, Naiara Moreira, Unai Bidarte, Marcelo Urbina, David Modrono. 1-6 [doi]
• Explicitly isolating data and computation in high level synthesis: the role of polyhedral frameworkRiccardo Cattaneo, Gabriele Pallotta, Donatella Sciuto, Marco D. Santambrogio. 1-6 [doi]
• Keynote 1 - From data to information to flowOskar Mencer. 1 [doi]
• Accelerating all-pairs shortest path using a message-passing reconfigurable architectureOsama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip Jones, Joseph Zambreno. 1-6 [doi]
• Statistical performance of the ARM cortex A9 accelerator coherency port in the xilinx zynq SoC for real-time applicationsAndrew Powell, Dennis Silage. 1-6 [doi]
• Accurate in-situ runtime measurement of energy per operation of system-on-chip on FPGASiddharth S. Bhargav, Rishvanth K. Prabakar, Young H. Cho. 1-8 [doi]
• A sparse VLIW instruction encoding scheme compatible with generic binariesAnthony Brandon, Joost Hoozemans, Jeroen van Straten, Arthur Francisco Lorenzon, Anderson Luiz Sartor, Antonio Carlos Schneider Beck, Stephan Wong. 1-7 [doi]
• An improved hardware design for matrix inverse based on systolic array QR decomposition and piecewise polynomial approximationL. Canche Santos, Alejandro Castillo Atoche, J. Vazquez Castillo, Omar Longoria-Gandaraz, Roberto Carrasco-Alvarez, J. Ortegon Aguilar. 1-6 [doi]
• FAUPU - A design framework for the development of programmable image processing architecturesMarc Reichenbach, Tobias Lieske, Steffen Vaas, Konrad Häublein, Dietmar Fey. 1-8 [doi]
• Message from chairsMaya Gokhale, Michael Hübner, René Cumplido. 1 [doi]
• A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliancesJose Fernando Zazo, Sergio López-Buedo, Yury Audzevich, Andrew W. Moore 0002. 1-6 [doi]
• FPGA implementation of the EKF algorithm for localization in mobile robotics using a unified hardware module approachLuis Contreras, Sérgio Cruz, José Mauricio S. T. Motta, Carlos H. Llanos. 1-6 [doi]
• Resource-saving compile flow for coarse-grained reconfigurable architecturesZhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao. 1-8 [doi]
• MiCAP: a custom reconfiguration controller for dynamic circuit specializationAmit Kulkarni, Kizheppatt Vipin, Dirk Stroobandt. 1-6 [doi]
• Achieving energy-efficiency on MPSoCs: performance and power optimizationsHongyuan Ding, Miaoqing Huang. 1-7 [doi]
• Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probesM. Ruizy, G. Suttery, Sergio López-Buedo, J. Ramosy, Jorge E. López de Vergara, Javier Aracil. 1-6 [doi]
• Hardware isolation technique for IRC-based botnets detectionFestus Hategekimana, Adil Tbatou, Christophe Bobda, Charles A. Kamhoua, Kevin A. Kwiat. 1-6 [doi]
• Using shadow pointers to trace C pointer values in FPGA circuitsJoshua S. Monson, Brad L. Hutchings. 1-6 [doi]
• Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systemsBruno A. Silva, Alexandre C. B. Delbem, Vanderlei Bonato, Pedro C. Diniz. 1-6 [doi]
• Buffering strategies for ultra high-throughput stream processingThaddeus Koehn, Peter Athanas. 1-7 [doi]
• Large-scale high-dimensional nearest neighbor search using flash memory with in-store processingSang-Woo Jun, Chanwoo Chung, Arvind. 1-8 [doi]
• A software configurable and parallelized coprocessor architecture for LQR controlPei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones. 1-8 [doi]
• Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAsAlfonso Rodriguez, Juan Valverde, Eduardo de la Torre. 1-7 [doi]
• A hybrid design for high performance large-scale sorting on FPGAAjitesh Srivastava, Ren Chen, Viktor K. Prasanna, Charalampos Chelmis. 1-6 [doi]
• Design and synthesis of reconfigurable control-flow structures for CGRAZoltán Endre Rákossy, Axel Acosta Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay. 1-8 [doi]
• Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAsVincent Mirian, Paul Chow. 1-8 [doi]
• GIMME2 - an embedded system for stereo vision and processing of megapixel images with FPGA-accelerationCarl Ahlberg, Fredrik Ekstrand, Mikael Ekström, Giacomo Spampinato, Lars Asplund. 1-8 [doi]
• A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano. 1-6 [doi]
• Aging effects on ring-oscillator-based physical unclonable functions on FPGAsStefan Gehrer, Sebastien Leger, Georg Sigl. 1-6 [doi]
• Polynomial multipliers for fully homomorphic encryption on FPGAC. Jayet-Griffon, M.-A. Cornelie, Paolo Maistri, Philippe Elbaz-Vincent, Régis Leveugle. 1-6 [doi]
• Feasibility of high level compiler optimizations in online synthesisLukas Johannes Jung, Christian Hochberger. 1-7 [doi]
• An architectural template for composing application specific datapaths at runtimeRico Backasch, Gerald Hempel, Christopher Blochwitz, Stefan Werner, Sven Groppe, Thilo Pionteck. 1-6 [doi]
• Scalable analytic placement for FPGA on GPGPURyan Pattison, Christian Fobel, Gary William Grewal, Shawki Areibi. 1-6 [doi]