Abstract is missing.
- Routing algorithm for multi-FPGA based systems using multi-point physical tracksQingshan Tang, Matthieu Tuna, Habib Mehrez. 2-8 [doi]
- FPGA-based HPC application design for non-expertsDavid Uliana, Krzysztof Kepa, Peter Athanas. 9-15 [doi]
- Visual exploration of changing FPGA architectures in the VTR projectKonstantin Nasartschuk, Rainer Herpers, Kenneth B. Kent. 16-22 [doi]
- An implementation of a distributed fault-tolerant mechanism for 2D mesh NoCsCésar A. M. Marcon, Alexandre M. Amory, Felipe T. Bortolon, Thais Webber, Thomas Volpato, Jader Munareto. 24-29 [doi]
- Performance modeling for designing NoC-based multiprocessorsTakashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura. 30-36 [doi]
- BaBaNoC: An asynchronous network-on-chip described in BalsaMatheus T. Moreira, Felipe G. Magalhaes, Matheus Gibiluka, Fabiano Hessel, Ney Laert Vilar Calazans. 37-43 [doi]
- Quota setting router architecture for quality of service in GALS NoCKazem Cheshmi, Mohammadreza Soltaniyeh, Siamak Mohammadi, Jelena Trajkovic. 44-50 [doi]
- FlexOE: A congestion-aware routing algorithm for NoCsOtavio Alcantara de Lima Junior, Virginie Fresse, Frédéric Rousseau. 51-57 [doi]
- Enforcing software engineering tools interoperability: An example with AADL subsetsVincent Gaudel, Frank Singhoff, Alain Plantec, Jérôme Hugues, Pierre Dissaux, Jérôme Legrand. 59-65 [doi]
- Rapid safety evaluation of hardware architectural designs compliant with ISO 26262Nico Adler, Stefan Otten, Markus Mohrhard, Klaus D. Müller-Glaser. 66-72 [doi]
- Embedded system verification through constraint-based schedulingOlfat El-Mahi, Gilles Pesant, Gabriela Nicolescu, Giovanni Beltrame. 73-79 [doi]
- Emulation-based design evaluation of reader/smart card systemsNorbert Druml, Manuel Menghin, Daniel Kroisleitner, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 80-86 [doi]
- Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codesPurushotham Murugappa, Vianney Lapotre, Amer Baghdadi, Michel Jézéquel. 87-93 [doi]
- A flexible framework for modeling and simulation of multipurpose wireless networksVinicius Bohrer, Ramon Fernandes, César A. M. Marcon, Thais Webber, Leticia B. Poehls, Ricardo M. Czekster, Fabiano Hessel. 94-100 [doi]
- SMASH: A heuristic methodology for designing partially reconfigurable MPSoCsRiccardo Cattaneo, Christian Pilato, Gianluca Durelli, Marco Domenico Santambrogio, Donatella Sciuto. 102-108 [doi]
- Seamless integration of HW/SW components in a HLS-based SoC design environmentTiago Rogério Mück, Antônio Augusto Fröhlich. 109-115 [doi]
- A framework for instruction encoding designs on embedded processorsRicardo Santos, Renan Marks, Renato Santos. 116-122 [doi]
- YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCsSilvia Lovergine, Antonino Tumeo, Oreste Villa, Fabrizio Ferrando. 123-129 [doi]
- Customizable RTOS to support communication infrastructures and to improve design space exploration in MPSoCsAlexandra Aguiar, Sergio Johann Filho, Felipe Gohring de Magalhaes, Fabiano Hessel. 130-135 [doi]
- MAMPSx: A design framework for rapid synthesis of predictable heterogeneous MPSoCsShakith Fernando, Firew Siyoum, Yifan He, Akash Kumar, Henk Corporaal. 136-142 [doi]