Table of Contents

• Is computer science dying?Alex Nicolau. [doi]
• Potential future research in computing: Heterogeneous systems, memory subsystems - Process-in-storage, or not to process-in-storage? That is the questionUri C. Weiser. [doi]
• Concurrent memory subsystem and application optimization for ASIP designJuan Fernando Eusse, Francisco Fernandez, Rainer Leupers, Gerd Ascheid. 1-10 [doi]
• Automatic recognition of computational kernels for platform-dependent code optimizationsMaria H. Rodriguez Blanco, Georg Reinke, Gerd Ascheid, Rainer Leupers. 11-20 [doi]
• Processes and actors: Translating Kahn processes to dataflow with firingGustav Cedersjo, Jörn W. Janneck. 21-30 [doi]
• Bard: A unified framework for managing soft timing and power constraintsConnor Imes, Henry Hoffmann. 31-38 [doi]
• Power models supporting energy-efficient co-design on ultra-low power embedded systemsVi Ngoc-Nha Tran, Brendan Barry, Phuong Hoai Ha. 39-46 [doi]
• Real-time tasks and voltage/frequency controller collaboration on low power energy operational systemsRawlinson S. Goncalves, Diego Q. Pinheiro, Eduardo Bezerra Valentin, Horacio A. B. F. de Oliveira, Raimundo S. Barreto. 47-54 [doi]
• numap: A portable library for low-level memory profilingManuel Selva, Lionel Morel, Kevin Marquet. 55-62 [doi]
• A bypass first policy for energy-efficient last level cachesJason Jong Kyu Park, Yongjun Park, Scott A. Mahlke. 63-70 [doi]
• Runtime support for adaptive power capping on heterogeneous SoCsYun Wu, Dimitrios S. Nikolopoulos, Roger F. Woods. 71-78 [doi]
• AccuRA: Accurate alignment of short reads on scalable reconfigurable acceleratorsSanthi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy. 79-87 [doi]
• Simulator calibration for accelerator-rich architecture studiesMochamad Asri, Ardavan Pedram, Lizy K. John, Andreas Gerstlauer. 88-95 [doi]
• Exploring system performance using elastic traces: Fast, accurate and portableRadhika Jagtap, Stephan Diestelhorst, Andreas Hansson, Matthias Jung 0001, Norbert Wehn. 96-105 [doi]
• CoolSim: Statistical techniques to replace cache warming with efficient, virtualized profilingNikos Nikoleris, Andreas Sandberg, Erik Hagersten, Trevor E. Carlson. 106-115 [doi]
• Genesys: Automatically generating representative training sets for predictive benchmarkingReena Panda, Xinnian Zheng, Shuang Song, Jee Ho Ryoo, Michael LeBeane, Andreas Gerstlauer, Lizy K. John. 116-123 [doi]
• Architecture exploration of a programmable neural network processor for embedded systemsWonyong Sung, Jinhwan Park. 124-131 [doi]
• Supporting composition in symbolic system synthesisKai Neubauer, Christian Haubelt, Michael Glaß. 132-139 [doi]
• Design productivity of a high level synthesis compiler versus HDLMaxime Pelcat, Cédric Bourrasset, Luca Maggiani, François Berry. 140-147 [doi]
• Multi-view consistency for infinitary regular languagesMaria Pittou, Stavros Tripakis. 148-155 [doi]
• A configurable SIMD architecture with explicit datapath for intelligent learningYifan He, Maurice Peemen, Luc Waeijen, Erkan Diken, Mattia Fiumara, Gerard K. Rauwerda, Henk Corporaal, Tong Geng. 156-163 [doi]
• Implications of non-volatile memory as primary storage for database management systemsNaveed Ul Mustafa, Adriè Armejach, Özcan Özturk, Adrián Cristal, Osman S. Unsal. 164-171 [doi]
• Improving performance in VLIW soft-core processors through software-controlled scratchpadsTiago T. Jost, Gabriel L. Nazar, Luigi Carro. 172-179 [doi]
• NanoStreams: Codesigned microservers for edge analytics in real timeGiorgis Georgakoudis, Charles Gillan, Ahmad Hassan, Umar I. Minhas, Ivor T. A. Spence, George Tzenakis, Hans Vandierendonck, Roger F. Woods, Dimitrios S. Nikolopoulos, Murali Shyamsundar, Paul Barber, Matthew Russell, Angelos Bilas, Stelios Kaloutsakis, Heiner Giefers, Peter W. J. Staar, Costas Bekas, Neil Horlock, Richard Faloon, Colin Pattison. 180-187 [doi]
• Evaluating physically unclonable functions on a large set of FPGAsSebastien Bellon, Claudio Favi, Miroslaw Malek, Marco Macchetti, Francesco Regazzoni. 188-195 [doi]
• Hardware-efficient index mapping for mixed radix-2/3/4/5 FFTsTomasz Patyk, Jarmo Takala. 196-201 [doi]
• On the modeling of error functions as high dimensional landscapes for weight initialization in learning networksJulius, Gopinath Mahale, T. Sumana, C. S. Adityakrishna. 202-210 [doi]
• Hybrid code description for developing fast and resource efficient image processing architecturesKonrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich. 211-218 [doi]
• Automated dataflow graph mergingNils Voss, Stephen Girdlestone, Oskar Mencer, Georgi Gaydadjiev. 219-226 [doi]
• High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platformsEndri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck. 227-234 [doi]
• Coarse grained reconfigurable architectures in the past 25 years: Overview and classificationMark Wijtvliet, Luc Waeijen, Henk Corporaal. 235-244 [doi]
• Empowering OpenMP with automatically generated hardwareArtur Podobas, Mats Brorsson. 245-252 [doi]
• Aggressively bypassing list scheduler for transport triggered architecturesHeikki O. Kultala, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala. 253-260 [doi]
• A hybrid ASIC/FPGA fault-tolerant artificial pancreasMichail S. Vavouras, Rui Policarpo Duarte, Antonino Armato, Christos-Savvas Bouganis. 261-267 [doi]
• From reversible logic to quantum circuits: Logic design for an emerging technologyRobert Wille, Anupam Chattopadhyay, Rolf Drechsler. 268-274 [doi]
• A strong arbiter PUF using resistive RAMSwaroop Ghosh, Rekha Govindaraj. 275-280 [doi]
• Racetrack memory-based encoder/decoder for low-power interconnect architecturesSuman Deb, Leibin Ni, Hao Yu, Anupam Chattopadhyay. 281-287 [doi]
• Transforming nanodevices to next generation nanosystemsMax Marcel Shulaker, Gage Hills, H.-S. Philip Wong, Subhasish Mitra. 288-292 [doi]
• Data centres for IoT applications: The M2DC approach (Invited paper)Michal Kierzynka, Ariel Oleksiak, Giovanni Agosta, Carlo Brandolese, William Fornaciari, Gerardo Pelosi, Micha vor dem Berge, Wolfgang Christmann, Stefan Krupop, Mariano Cecowski, Robert Plestenjak, Justin Cinkelj, Mario Porrmann, Jens Hagemeyer, Rene Griessl, Meysam Peykanu, Lennart Tigges, Loïc Cudennec, Thierry Goubier, Jean-Marc Philippe, Sven Rosinger, Daniel Schlitt, Christian Pieper, Chris Adeniyi-Jones, Udo Janssen, Luca Ceva. 293-299 [doi]
• Performance and energy evaluation of spark applications on low-power SoCsIoannis Stamelos, Dimitrios Soudris, Christoforos Kachris. 300-305 [doi]
• TULIPP: Towards ubiquitous low-power image processing platformsTobias Kalb, Lester Kalms, Diana Göhringer, Carlota Pons, Fabien Marty, Ananya Muddukrishna, Magnus Jahre, Per Gunnar Kjeldsberg, Boitumelo Ruf, Tobias Schuchert, Igor Tchouchenkov, Carl Ehrenstrahle, Flemming Christensen, Antonio Paolillo, Christian Lemer, Guillaume Bernard, François Duhem, Philippe Millet. 306-311 [doi]
• Performance-power exploration of software-defined big data analytics: The AEGLE cloud backendGeorgios Zervakis, Sotirios Xydis, Dimitrios Soudris. 312-319 [doi]
• Safe cooperative CPS: A V2I traffic management scenario in the SafeCOP projectAlessio Agneessens, Francesco Buemi, Stefano Delucchi, Massimo Massa, Giovanni Agosta, Alessandro Barenghi, Carlo Brandolese, William Fornaciari, Gerardo Pelosi, Enrico Ferrari, Dajana Cassioli, Luigi Pomante, Leonardo Napoletani, Luciano Bozzi, Carlo Tieri, Maurizio Mongelli. 320-327 [doi]
• Enabling indoor object localization through Bluetooth beacons on the RADIO robot platformFynn Schwiegelshohn, Philipp Wehner, Florian Werner 0002, Diana Göhringer, Michael Hübner. 328-333 [doi]
• Perspectives on system-level MPSoC design space explorationAndy Pimentel. 335 [doi]
• A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architecturesKostas Siozios, Ioannis Savidis, Dimitrios Soudris. 336-341 [doi]
• MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architecturesMaria Mendez Real, Philipp Wehner, Jens Rettkowski, Vincent Migliore, Vianney Lapotre, Diana Göhringer, Guy Gogniat. 342-347 [doi]
• A quasi-cycle accurate timing model for binary translation based instruction set simulatorsSören Schreiner, Ralph Görgen, Kim Grüttner, Wolfgang Nebel. 348-353 [doi]
• XL-STaGe: A cross-layer scalable tool for graph generation, evaluation and implementationPedro B. Campos, Nizar Dahir, Colin Bonney, Martin Trefzer, Andy M. Tyrrell, Gianluca Tempesti. 354-359 [doi]
• A hybrid approach for mapping and scheduling on heterogeneous multicore systemsAndreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikolaos Voros. 360-365 [doi]
• Black box ESL power estimation for loosely-timed TLM modelsGereon Onnebrink, Rainer Leupers, Gerd Ascheid, Stefan Schürmans. 366-371 [doi]
• An OpenCL-based framework for rapid virtual prototyping of heterogeneous architecturesEfstathios Sotiriou-Xanthopoulos, Leonard Masing, Kostas Siozios, George Economakos, Dimitrios Soudris, Jürgen Becker. 372-377 [doi]
• Incorporating rapid design assembly into a virtual prototyping environmentRyan Marlow, Shenghou Ma, Kevin Lee, Andrew Love, Peter M. Athanas. 378-383 [doi]