Table of Contents

• Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integrationMichael Hübner, Jürgen Becker. 1-4 [doi]
• Formal verification for real-world designsValeria Bertacco. 5 [doi]
• Robust low power computing in the nanoscale eraTodd M. Austin. 6 [doi]
• The re-definition of low power design for HPC: a paradigm shiftReiner W. Hartenstein. 7 [doi]
• High performance silicon MEMS for niche market applicationsAndrès E. Lagos. 8 [doi]
• Run-time reconfigurabilility and other future trendsJürgen Becker, Michael Hübner. 9-11 [doi]
• Low maintenance verificationValeria Bertacco. 12 [doi]
• Razor: a low-power pipeline based on circuit-level timing speculationTodd M. Austin. 13 [doi]
• REDEFIS: a system with a redefinable instruction set processorVictor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki Murakami. 14-19 [doi]
• Asynchronous circuit design on reconfigurable devicesR. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis. 20-25 [doi]
• FPGA architecture for static background subtraction in real timeJozias Oliveira, André Printes, R. C. S. Freire, Elmar U. K. Melcher, Ivan S. S. Silva. 26-31 [doi]
• Implementation of dispatching algorithms for elevator systems using reconfigurable architecturesDaniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón, Rudi van Els, Renato P. Almeida. 32-37 [doi]
• Dynamic task binding for hardware/software reconfigurable networksThilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich. 38-43 [doi]
• Infrastructure for dynamic reconfigurable systems: choices and trade-offsLeandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes. 44-49 [doi]
• Mapping of image processing systems to FPGA computer based on temporal partitioning and design space explorationPaulo Sérgio B. do Nascimento, Manoel Eusebio de Lima, Stelita M. da Silva, Jordana L. Seixas. 50-55 [doi]
• Ant colony based routing architecture for minimizing hot spots in NOCsMasoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi. 56-61 [doi]
• Application driven traffic modeling for NoCsLeonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes. 62-67 [doi]
• Area and performance optimization of a generic network-on-chip architectureMário P. Véstias, Horácio C. Neto. 68-73 [doi]
• An ultra low-power class-AB sinh integratorSandro A. P. Haddad, Wouter A. Serdijn. 74-79 [doi]
• Ultra low-voltage ultra low-power CMOS threshold voltage referenceLuis H. C. Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. V. Noije. 80-82 [doi]
• A test chip for automatic MOSFET mismatch characterizationHamilton Klimach, Márcio C. Schneider, Carlos Galup-Montoro. 83-88 [doi]
• Power constrained design optimization of analog circuits based on physical gm/ID characteristicsAlessandro Girardi, Sergio Bampi. 89-93 [doi]
• Bias circuit design for low-voltage cascode transistorsPablo Aguirre, Fernando Silveira. 94-97 [doi]
• A differential switched-capacitor amplifier with programmable gain and output offset voltageFabio Lacerda, Stefano Pietri, Alfredo Olmos. 98-102 [doi]
• 4GHz continuous-time bandpass delta-sigma modulator for directly high IF A/D conversionA. A. Mariano, Dominique Dallet, Yann Deval, Jean-Baptiste Begueret. 103-107 [doi]
• A general domain CMOS companding integratorAna Isabela Araújo Cunha, Ali M. Niknejad. 108-112 [doi]
• Energy aware multiple clock domain scheduling for a bit-serial, self-timed architectureHeiner Giefers, Achim Rettberg. 113-118 [doi]
• Aspect-oriented design in systemC: implementation and applicationsDavid Déharbe, Sergio Medeiros. 119-124 [doi]
• SAEPTUM: verification of ::::ELAN:::: hardware specifications using the proof assistant ::::PVS::::Mauricio Ayala-Rincón, Thomas Mailleux Santana. 125-130 [doi]
• A fast SAT solver algorithm best suited to reconfigurable hardwareRomanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.. 131-136 [doi]
• Fast disjoint transistor networks from BDDsLeomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis. 137-142 [doi]
• MDA-based approach for embedded software generation from a UML/MOF repositoryFrancisco Assis Moreira Nascimento, Marcio F. da S. Oliveira, Marco A. Wehrmeister, Carlos Eduardo Pereira, Flávio Rech Wagner. 143-148 [doi]
• Hardware support in a middleware for distributed and real-time embedded applicationsElias Teodoro Silva Jr., Flávio Rech Wagner, Edison Pignaton de Freitas, Carlos Eduardo Pereira. 149-154 [doi]
• Cache performance impacts for stack machines in embedded systemsAntonio Carlos Schneider Beck, Mateus B. Rutzig, Luigi Carro. 155-160 [doi]
• Exploiting general coefficient representation for the optimal sharing of partial products in MCMsEduardo A. C. da Costa, Paulo F. Flores, José Monteiro. 161-166 [doi]
• A cell library for low power high performance CMOS voltage-mode quaternary logicRicardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro. 167-172 [doi]
• On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitivesKatarina Paulsson, Michael Hübner, Jürgen Becker. 173-178 [doi]
• ByZFAD: a low switching activity architecture for shift-and-add multipliersMohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi. 179-183 [doi]
• Single event transients in dynamic logicGilson I. Wirth, Ivandro Ribeiro, Michele G. Vieira, Fernanda Gusmão de Lima Kastensmidt. 184-189 [doi]
• A cryptography core tolerant to DFA fault attacksCarlos Roberto Moratelli, Érika F. Cota, Marcelo Lubaszewski. 190-195 [doi]
• Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gatesRodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis. 196-201 [doi]
• Evaluation of SEU and crosstalk effects in network-on-chip switchesArthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota. 202-207 [doi]
• Using a software testing technique to identify registers for partial scan implementationMargrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski. 208-213 [doi]
• Using NEXUS compliant debuggers for real time fault injection on microprocessorsAndré V. Fidalgo, Manuel G. Gericota, Gustavo R. Alves, José M. Ferreira. 214-219 [doi]
• Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealingRenato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis. 220-225 [doi]
• Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICsDaniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali. 226-231 [doi]
• A band-pass Gm-C Filter design based on gm/ID methodology and characterizationFernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi. 232-237 [doi]