Table of Contents

• A methodology for the automatic design of operational amplifiers including yield optimizationLucas C. Severo, Alessandro Girardi. 1-6 [doi]
• A 14b threshold configurable dynamically latched comparator for SAR ADCsTony Forzley, Ralph Mason. 1-5 [doi]
• Voltage Regulation System for UHF RFID TagsJose Luis Garcia-Gervacio, Agustin L. Herrera May, Gregorio Zamora Mejia, Jaime Martínez-Castillo, Alejandro Díaz-Sánchez. 1-6 [doi]
• A CMOS bandgap reference circuit with a temperature coefficient adjustment blockEder Issao Ishibe, Joao Navarro Soares. 1-6 [doi]
• A 400 MHz reconfigurable injection-locking based RC oscillator for ASK/FSK modulationKarolinne Brito, Fernando Rangel de Sousa, Victor Ariel Leal Sobral, Robson Nunes de Lima, Raimundo Carlos Silvério Freire. 1-4 [doi]
• Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approachesIuri A. C. Gomes, Fernanda Gusmão de Lima Kastensmidt. 1-6 [doi]
• Hardware design for the 32×32 IDCT of the HEVC video coding standardRuhan Conceicao, J. Claudio Souza, Ricardo Jeske, Marcelo Schiavon Porto, Júlio C. B. de Mattos, Luciano Volcan Agostini. 1-6 [doi]
• A 433/915-MHz class AB discrete power amplifier based on multiresonant circuitsFabricio G. S. Silva, Robson Nunes de Lima, Raimundo C. S. Freire. 1-6 [doi]
• Real-time digital modulation classification based on Support Vector MachinesEdson Sorato, Eduardo P. Fronza, Paulo R. F. M. M. Barbosa, Jose Luis Guntzel, Adalbery R. Castro, Aldebaro Klautau. 1-6 [doi]
• An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCsJohanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum. 1-6 [doi]
• Hybrid filter for high-power converter systemsGuilherme H. K. Martini, João Alberto Fabro. 1-6 [doi]
• PTAT CMOS current sources mismatch over temperatureAndré Luiz Aita, Cesar Ramos Rodrigues. 1-4 [doi]
• Efficient memory access in 2D Mesh NoC architectures using high bandwidth routersJan Heisswolf, Simon Bischof, Michael Rückauer, Jürgen Becker. 1-6 [doi]
• Design of crest factor reduction techniques based on clipping and filtering for wireless communications systemsPedro F. G. da Silva, Eduardo G. de Lima. 1-5 [doi]
• An RF-powered temperature sensor designed for biomedical applicationsGustavo Campos Martins, Fernando Rangel de Sousa. 1-6 [doi]
• Parallel prefix adder design using quantum-dot cellular automataKim A. Escobar, Renato P. Ribas. 1-6 [doi]
• Delay model for static CMOS complex gatesFelipe S. Marranghello, André Inácio Reis, Renato P. Ribas. 1-6 [doi]
• An efficient FPGA implementation in quantum-dot cellular automataAbner Luis Panho Marciano, Andre B. Oliveira, José Augusto Miranda Nacif, Omar P. Vilela Neto. 1-6 [doi]
• Spin diode network synthesis using functional compositionMayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis. 1-6 [doi]
• A novel system on chip for software-defined, high-speed OFDM signal processingJoachim Meyer, Michael Dreschmann, Djorn Karnick, Philipp C. Schindler, Wolfgang Freude, Juerg Leuthold, Jürgen Becker. 1-6 [doi]
• H2A: A hardened asynchronous network on chipJulian J. H. Pontes, Ney Calazans, Pascal Vivet. 1-6 [doi]
• On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculationIsmael Seidel, Bruno George de Moraes, Andre Beims Brascher, José Luís Güntzel. 1-6 [doi]
• Synthesis of a narrow-band Low Noise Amplifier in a 180 nm CMOS technology using Simulated Annealing with crossover operatorTiago Oliveira Weber, Sergio Chaparro, Wilhelmus A. M. Van Noije. 1-5 [doi]
• CMOS smart temperature sensors for RFID applicationsJuan Pablo Martinez Brito, Alain Rabaeijs. 1-6 [doi]
• m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliersLeandro Zafalon Pieper, Eduardo A. C. da Costa, José C. Monteiro. 1-6 [doi]
• Energy-speed exploration for very-wide range of dynamic V-F scalingKleber Stangherlin, Sergio Bampi. 1-6 [doi]
• Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protectionJohanna Sepúlveda, Guy Gogniat, Ricardo Pires, Wang Jiang Chau, Marius Strum. 1-6 [doi]
• Low-Power/Low-Voltage analog front-end for LF passive RFID tag systemsFernando Paixão Cortes, Guilherme Freitas, Henrique Luiz Andrade Pimentel, Juan Pablo Martinez Brito, Fernando Chavez. 1-6 [doi]
• Power consumption analysis in static CMOS gatesAlberto Wiltgen, Kim A. Escobar, André Inácio Reis, Renato P. Ribas. 1-6 [doi]
• Analytical logical effort formulation for minimum active area under delay constraintsCaio G. P. Alegretti, Vinícius Dal Bem, Renato P. Ribas, André Inácio Reis. 1-6 [doi]
• Implementation of split-radix FFT pruning for the reduction of computational complexity in OFDM based cognitive radio systemSungHa Jung, Lim Myoungseob, Yihu Xu, Dae Hyun Jo. 1-5 [doi]
• Global routing congestion reduction with cost allocation look-aheadLeandro Nunes, Ricardo Reis. 1-5 [doi]
• A methodology to evaluate the aging impact on flip-flops performanceCicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas. 1-6 [doi]
• Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancyYan Ghidini, Matheus T. Moreira, Lucas Brahm, Thais Webber, Ney Calazans, César A. M. Marcon. 1-6 [doi]
• Synthesis of threshold logic gates to nanoelectronicsAugusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis. 1-6 [doi]
• Gray encoded fixed-point LMS adaptive filter architecture for the harmonics power line interference cancellingEduardo A. C. da Costa, Sérgio J. M. de Almeida, Monica Matzenauer. 1-6 [doi]
• A new code compression algorithm and its decompressor in FPGA-based hardwareWanderson Roger Azevedo Dias, Edward David Moreno, Isaac Nattan Palmeira. 1-6 [doi]
• A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulationChristoph Roth, Harald Bucher, Simon Reder, Florian Buciuman, Oliver Sander, Jürgen Becker. 1-6 [doi]
• Read-polarity-once Boolean functionsVinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis. 1-6 [doi]
• A resistorless switched bandgap voltage reference with offset cancellationHamilton Klimach, Arthur Liraneto Torres Costa, Moacir Fernandes Cortinhas Monteiro, Sergio Bampi. 1-5 [doi]
• Improving the methodology to build non-series-parallel transistor arrangementsVinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.. 1-6 [doi]
• Temporal noise analysis and measurements of CMOS active pixel sensor operating in time domainFernando de Souza Campos, Jose Alfredo Covolan Ulson, Jacobus W. Swart, M. Jamal Deen, Ognian Marinov, Dib Karam. 1-5 [doi]