Abstract is missing.
- A temperature-aware analysis of latched comparators for smart vehicle applicationsAdriano V. Fonseca, Rachid El Khattabi, William A. Afshari, Fernando A. P. Barúqui, Carlos F. T. Soares, Pietro Maris Ferreira. 1-6 [doi]
- A radio-frequency real-time spectrum sensor based on an analog signal processing magnitude calculatorJulien Orlando, Francois Rivet, Yann Deval. 7-10 [doi]
- Low power IEEE 802.11ah receiver system-level design aiming for IoT applicationsNelson Andrade, Pedro Toledo, Gabriel Teofilo Neves Guimaraes, Hamilton Klimach, Helga Dornelas, Sergio Bampi. 11-16 [doi]
- A novel hybrid polarization-quadrature pixel cluster for local light angle and intensity detectionFrancelino Freitas Carvalho, Alexandre Kennedy Pinto Souza, Carlos Augusto de Moraes Cruz. 17-23 [doi]
- Modeling of a MOS ultralow voltage oscillator: experimental resultsAntonio C. C. Telles, Jose Antenor Pomilio, Saulo Finco. 24-29 [doi]
- Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processingCamila de Matos Alonso, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi. 30-35 [doi]
- Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standardGustavo Sanchez, Filipo Mór, Luciano Volcan Agostini, César A. M. Marcon. 36-40 [doi]
- Low-power multi-size HEVC DCT architecture proposal for QFHD video processingLuana Vieira Martinez Bonatto, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi. 41-46 [doi]
- Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architectureFábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi. 47-52 [doi]
- Hardware module for low-resource and real-time stereo vision engine using semi-global matching approachLucas F. S. Cambuim, João Paulo Fernandes Barbosa, Edna Natividade da Silva Barros. 53-58 [doi]
- A security-aware routing implementation for dynamic data protection in zone-based MPSoCJohanna Sepúlveda, Ramon Fernandes, César A. M. Marcon, Daniel Florez, Georg Sigl. 59-64 [doi]
- Secure admission and execution of applications in many-core systemsLuciano L. Caimi, Vinicius Fochi, Eduardo Wächter, Daniel Munhoz, Fernando Gehm Moraes. 65-71 [doi]
- Latency reduction of fault-tolerant NoCs by employing multiple pathsRonaldo T. P. Milfont, Rafael Goncalves Mota, João M. Ferreira, Paulo C. Cortez, César A. M. Marcon, Daniel A. B. Tavares, Jarbas A. N. Silveira. 72-78 [doi]
- Hardware and software infrastructure to implement many-core systems in modern FPGAsFelipe T. Bortolon, Fernando Gehm Moraes. 79-83 [doi]
- Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in freeRTOS applicationsÁdria Barros de Oliveira, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt. 84-89 [doi]
- Estimation methods for static noise margins in CMOS subthreshold logic circuitsFelipe T. Bortolon, Fernando Gehm Moraes, Matheus T. Moreira, Sergio Bampi. 90-95 [doi]
- A SVM optimization tool and FPGA system architecture applied to NMPCCarlos Eduardo Santos, Leandro dos Santos Coelho, Renato Coral Sampaio, Ricardo P. Jacobi, Helon V. H. Ayala, Carlos H. Llanos. 96-102 [doi]
- Sleep convention logic isochronic fork: an analysisRicardo A. Guazzelli, Matheus T. Moreira, Walter Lau Neto, Ney Laert Vilar Calazans. 103-109 [doi]
- A class-J power amplifier for 5G applications in 28nm CMOS FD-SOI technologyTony Hanna, Nathalie Deltimple, Sébastien Fregonese. 110-113 [doi]
- A SiGe HBT limiting amplifier for fast switching of mm-wave super-regenerative oscillatorsHatem Ghaleb, Guido Belfiore, Corrado Carta, Frank Ellinger. 114-119 [doi]
- An analog RF fully differential common mode controlled delay line in 28nm FDSOI technologyVictor Vaillant, François Rivet. 120-124 [doi]
- Development of microtransformers using MCM and electronic packaging technologiesM. M. Rocha, Antonio C. C. Telles, R. C. Teixeira. 125-128 [doi]
- High-impedance multi-conductor transmission-lines for integrated applications at millimeter-wave frequencyPaolo Valerio Testa, M. V. Thayyil, Guido Belfiore, C. Carta, Frank Ellinger. 129-135 [doi]
- A pixel concept that simultaneously enables high dynamic range, high sensitivity and operation in intense backgroundsP. N. A. Belmonte, L. M. Chaves, D. W. de Lima Monteiro. 136-142 [doi]
- Segmented spline hardware design for high dynamic range video pre-processorAlex Borges, Luciano A. Braatz, Bruno Zatt, Marcelo Schiavon Porto, Guilherme Corrêa. 143-148 [doi]
- Block matching hardware architecture for SATD-based successive eliminationLuiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel. 149-154 [doi]
- Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDEAndré Beims Bräscher, Ismael Seidel, José Luís Güntzel. 155-161 [doi]
- Efficient hardware implementation of morphological reconstruction based on sequential reconstruction algorithmOscar Anacona-Mosquera, George Teodoro, Gustavo Vinhal, Ricardo P. Jacobi, Renato Coral Sampaio, Carlos H. Llanos. 162-167 [doi]
- A power-predictive environment for fast and power-aware ASIC-based FIR filter designGuilherme Paim, Rafael S. Ferreira, Leandro M. G. Rocha, Eduardo A. C. da Costa, Tiago Giacomelli Alves, Sergio Bampi. 168-173 [doi]
- CAM/TCAM - NML: (ternary) content addressable memory implemented with nanomagnetic logicAmanda F. Fonseca, Douglas L. Willian, Thiago Rodrigues B. S. Soares, Luiz G. C. Melo, Omar P. Vilela Neto. 174-179 [doi]
- A 34fJ/conversion-step 10-bit 6.66MS/s SAR ADC with built-in digital calibration in 130nm CMOSFelipe Makara, Lucas Mangini, André A. Mariano. 180-184 [doi]
- A decoder with soft decoding capability for high-rate generalized concatenated codes with applications in non-volatile flash memoriesJens Spinner, Jürgen Freudenberger. 185-190 [doi]
- Exploiting cache locality to speedup register clusteringTiago Augusto Fontana, Sheiny Almeida, Renan Netto, Vinicius S. Livramento, Chrystian Guth, Laércio Lima Pilla, José Luís Güntzel. 191-197 [doi]
- An efficient, low-cost ECC approach for critical-application memoriesFelipe Silva, Otávio Lima, Walter Freitas, Fabian Vargas, Jarbas Silveira, César A. M. Marcon. 198-203 [doi]
- Simplified model for automatic QCA circuitry verificationLuiz Henrique Borges Sardinha, Omar Paranaiba Vilela Neto, Vitor Buxbaum Orlandi, Sérgio Vale Aguiar Campos. 204-209 [doi]
- Mitigation of aging effects through selective time-borrowing and alternative path activationAndrei Silva, Frank Sill. 210-216 [doi]