Table of Contents

• Efficient Thread Tuning for Asymmetric MulticoresMarcelo K. Moori, Hiago Mayk G. de A. Rocha, Arthur Francisco Lorenzon, Antonio Carlos Schneider Beck. 1-5 [doi]
• A 9.78-ENOB 10 MS/s SAR ADC with a Common Mode Compensation Technique in a 28nm CMOS NodeJorge Angarita Pérez, Nicolas Orcasitas García, Hugo D. Hernández, Javier Ardila. 1-5 [doi]
• Evaluating the Resilience of the Approximate Parallel Prefix Adder (AxPPA) Against Hardware Trojan Horse InjectionEloisa Barros, Morgana Macedo Azevedo da Rosa, Rodrigo Lopes, Leonardo Antonietti, Eduardo A. C. da Costa, Rafael Soares. 1-5 [doi]
• Design of Low-Power 5.8-GHz ULV LNTAs using Normalized Biasing MetricVanessa M. Da F. Botinelly, Filipe F. Caetano, Pietro M. Ferreira, Osamu Saotome, Lucas Compassi Severo. 1-5 [doi]
• Voltage Coefficient of Resistance Effect in the Harmonic Distortion of Active-RC Continuous-Time Sigma-Delta ModulatorsTawan Chrysther dos Santos, Alessandro Gonçalves Girardi, Paulo César Comassetto de Aguirre. 1-5 [doi]
• Deep Nibble: A 4-bit Number Format for Efficient DNN Training and Inference in FPGALuiz Fernando Heidrich Duarte, George B. Nardes, Wesley Grignani, Douglas R. Melo, Cesar A. Zeferino. 1-5 [doi]
• An evolutionary search for energy recovery opportunities in partially reversible FCN circuitsBernardo N. Gomes, Marco T. D. Sousa, Jeferson F. Chaves, Omar P. Vilela Neto. 1-5 [doi]
• Enabling Programmable Data Planes with C++ and High-Level Synthesis for Custom Packet ForwardingNathan Guimarães, Mateus Saquetti, Pablo Rodrigues, Weverton Cordeiro, José Rodrigo Azambuja. 1-5 [doi]
• Layout Design of an Asynchronous Time-Based Image Sensor with Shared DVS ModuleVictor R. R. de Oliveira, Mirella M. de O. Carneiro, Fernanda D. V. R. Oliveira, Fernando Antonio Pinto Barúqui, José Gabriel R. C. Gomes. 1-5 [doi]
• A Real-Time UHD 4K Hardware for VVC Affine Linear Equation System SolvingDenis Maass, Marcello M. Muñoz, Murilo R. Perleberg, Luciano Agostini, Marcelo Schiavon Porto. 1-5 [doi]
• Image Classification CNNs using the FINN Engine for SRAM-based APSoC in Satellite ApplicationsArthur F. Ely, Fabio Benevenuti, Guilherme Korol, Antonio Carlos S. Beck, José Rodrigo Azambuja, Fernanda Lima Kastensmidt. 1-5 [doi]
• Investigating the Influence of Process Variability on Asymmetric Multicore ProcessorsThiago Dos Santos Gonçalves, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon. 1-5 [doi]
• AxMOD: VLSI Modular Reduction Design Exploring Approximate Arithmetic UnitsLourenço Mulling, Morgana Macedo Azevedo da Rosa, Rafael Soares, Eduardo A. C. da Costa. 1-5 [doi]
• A Divide-by-1.5/2 Prescaler Utilizing Double Data Rate TechniqueLucas Daudt Franck, João Navarro, João Paulo Carmo. 1-5 [doi]
• Design and Evaluation of a 10 GHz LNA with Balun and Diodes for HBM and CDM ESD Protection in 28 nm CMOS FD-SOIThalis Da C. Guedes, Johan Bourgeat, Manuel J. Barragán, Jean-Marc Duchamp, Philippe Ferrari. 1-5 [doi]
• Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque SwitchingZhenghan Fang, Lirida Naviner, Wen Wang, Wei Le, Hao Cai. 1-5 [doi]
• A Dual-Kernel Size-Configurable Gaussian Filter ArchitectureMarcio Monteiro, Ismael Seidel, José Luís Güntzel, Mateus Grellert, Leonardo Bandeira Soares, Cristina Meinhardt. 1-5 [doi]
• Robustness Analysis of Atomic Silicon Quantum Dot Logic GatesArthur M. Fortini, João Gabriel O. Bicalho, Omar P. Vilela Neto, Maria D. Vieira, José Augusto Miranda Nacif, Ricardo S. Ferreira 0001. 1-5 [doi]
• A 5-V 125-kHz Fourth-Order Continuous-Time Sigma-Delta Modulator in 130-nm BCD TechnologyRenan D. P. de Oliveira, Tawan Chrysther dos Santos, Matheus B. S. Carvalho, Cristian Muller, Alessandro Gonçalves Girardi, Lucas Compassi Severo, Paulo César Comassetto de Aguirre. 1-5 [doi]
• Bit-Width Optimized Transposition Buffer Design for the AV1 2D-DCT TransformJelson Rodrigues, Jones Goebel, Luciano Agostini, Bruno Zatt, Marcelo Schiavon Porto. 1-5 [doi]
• A Nanomagnetic Logic based processorLuís Fernando Miki, Laysson Oliveira Luz, José Augusto Miranda Nacif, Ricardo S. Ferreira 0001, Omar P. Vilela Neto. 1-5 [doi]
• The Digital-Based Operational Transconductance Amplifier: Evolution and PerspectivePedro Toledo, Sergio Bampi, Paolo Crovetti. 1-7 [doi]
• Joint Computation and Communication Analysis of Hard Real-Time Applications in ManycoresAnderson R. P. Domingues, Lucas Damo, Sergio Johann Filho, Fernando Gehm Moraes. 1-5 [doi]
• Enhancing Manycore Lifetime Through Reinforcement Learning Task Mapping and MigrationIaçanã I. Weber, Vitor Balbinot Zanini, Fernando Gehm Moraes. 1-5 [doi]
• TARA: Enhancing Real-Time Network Traffic Classification with Hardware Virtual LayersJulio Costella Vicenzi, Michael Guilherme Jordan, Guilherme Korol, Tiago Knorst, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 1-5 [doi]
• Computationally-Efficient Neural Image Compression Using Asymmetric AutoencodersLeonardo Augusto, Thiago L. T. da Silveira, Mateus Grellert. 1-5 [doi]
• Exploring Approximate Adders for an Energy-Efficient Pre-Processing Pan-Tompkins Algorithm VLSI DesignLéo Ribeiro, Morgana Macedo Azevedo da Rosa, Rafael Soares, Eduardo A. C. da Costa. 1-5 [doi]
• A Machine Learning Approach for Traffic Anomaly Detection in NoC-based ManycoresAngelo Elias Dalzotto, Fernando Gehm Moraes. 1-5 [doi]
• Impact on Delay, Power and Area of Machine Learning-based Approximate Logic SynthesisJoão Carlos Prats Ramos, Naiara Sachetti, Augusto Andre Souza Berndt, Jônata Tyska Carvalho, Cristina Meinhardt. 1-5 [doi]
• ADARE: Adaptive Resource Provisioning in Multi-FPGA Edge EnvironmentsIan Kersz, Henry Piceni, Michael Guilherme Jordan, José Rodrigo Azambuja, Fernanda Lima Kastensmidt, Antonio Carlos S. Beck. 1-5 [doi]
• NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-ChipAnderson I. Silva, Altamiro Susin, Fernanda L. Kastensmidt, Antonio Carlos S. Beck, José Rodrigo Azambuja. 1-5 [doi]
• Early Neutron Reliability Assessment of an Arm Cortex-M4 through Emulated Fault InjectionLeonardo R. Gobatto, Fabio Benevenuti, Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, José Rodrigo Azambuja. 1-5 [doi]
• All-GaN Integrated Overcurrent Protection Circuit Using Only Enhancement-mode p-GaN DevicesNataly Pozo, Luis-Miguel Prócel, Lionel Trojman. 1-5 [doi]
• EAVREF: An Evolutionary Algorithm Based Tool for Low-Power CMOS Voltage Reference DesignsAna Italiano, Luciana Almeida, Thiago Brito, Mariane R. Petraglia, Fabián Olivera. 1-5 [doi]
• A Semi-Automated Sizing Tool for CMOS Analog Building Blocks Integrated into EDA EnvironmentRodrigo S. Moraes, Lucas Compassi Severo. 1-5 [doi]
• FPGAs for Network Function Virtualization: Challenges in Placement and PartitioningVictor Sberse Guerra, Gabriel Luca Nazar. 1-5 [doi]
• Hardening a RISC-V Softcore for Embedded Aerospace Applications in SRAM-based FPGAEduardo Marañon Aguilar, Fabio Benevenuti, Fernanda Lima Kastensmidt. 1-5 [doi]
• A Hardware-Friendly Acceleration of VVC Affine Motion Estimation Using Decision TreesRamiro Viana, Marta Loose, Rafael S. Ferreira, Marcelo Schiavon Porto, Guilherme Corrêa 0001, Luciano Agostini. 1-5 [doi]
• Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by PartitioningEsther Goudet, Luis Peña Treviño, Gutemberg G. dos Santos Júnior, Sayah El Hajji, Fabio Sureau, Lirida Naviner, Jean-Marc Daveau, Philippe Roche. 1-5 [doi]