Abstract is missing.
- Terminal optimization analysis for functional block re-useStephen E. Krufka, Phillip Christie. 3-8 [doi]
- Getting more out of Donath s hierarchical model for interconnect predictionJoni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout. 9-16 [doi]
- Optimized pin assignment for lower routing congestion after floorplanning phaseTianpei Zhang, Sachin S. Sapatnekar. 17-21 [doi]
- FPGA interconnect planningAmit Singh, Malgorzata Marek-Sadowska. 23-30 [doi]
- The X architecture: not your father s diagonal wiringSteven L. Teig. 33-37 [doi]
- Estimation needs for future networking systems interconnectSudhakar Muddu. 41-44 [doi]
- Scaling trends of on-chip Power distribution noiseAndrey V. Mezhiba, Eby G. Friedman. 47-53 [doi]
- Technology trends in power-grid-induced noiseSani R. Nassif, Onsi Fakhouri. 55-59 [doi]
- Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnectsSeongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim. 61-68 [doi]
- Reconfigurable interconnect for next generation systemsIngrid Verbauwhede, M.-C. Frank Chang. 71-74 [doi]
- Early probabilistic noise estimation for capacitively coupled interconnectsMurat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda. 77-83 [doi]
- Refined single trunk tree: a rectilinear steiner tree generator for interconnect predictionHongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng. 85-89 [doi]
- Stochastic wire length sampling for cycle time estimationMuzammil Iqbal, Ahmed Sharkawy, Usman Hameed, Phillip Christie. 91-96 [doi]
- Wire layer geometry optimization using stochastic wire samplingRaymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie. 97-102 [doi]
- Interconnect exploration for future wire dominated technologiesAntonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex. 105-106 [doi]