Abstract is missing.
- Interconnection lengths and delays estimation for communication links in FPGAsTerrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk. 1-10 [doi]
- Efficient tiling patterns for reconfigurable gate arraysSumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger. 11-18 [doi]
- Timing optimization in logic with interconnectArkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny. 19-26 [doi]
- Revisiting fidelity: a case of elmore-based Y-routing treesTuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta. 27-34 [doi]
- Multi-core architectures and streaming applicationsGerard J. M. Smit, André B. J. Kokkeler, Pascal T. Wolkotte, Marcel D. van de Burgwal. 35-42 [doi]
- Parallel vs. serial on-chip communicationRostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar. 43-50 [doi]
- Global interconnections in FPGAs: modeling and performance analysisTerrence S. T. Mak, Crescenzo D Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk. 51-58 [doi]
- Circuit and physical design of the MDGRAPE-4 on-chip network linksDuraid Madina, Makoto Taiji. 59-64 [doi]
- The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalkBasel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alexandre Yakovlev, Gordon Russell. 65-72 [doi]
- Sidewinder: a scalable ILP-based routerJin Hu, Jarrod A. Roy, Igor L. Markov. 73-80 [doi]
- The next resource war: computation vs. communicationSimon W. Moore, Daniel Greenfield. 81-86 [doi]
- Rent s rule and parallel programs: characterizing network traffic behaviorWim Heirman, Joni Dambre, Dirk Stroobandt, Jan M. Van Campenhout. 87-94 [doi]