Table of Contents

• Message from the General ChairSung-Mo Kang. [doi]
• Message from the Technical Program ChairDong S. Ha. [doi]
• Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platformAmir Hosein Kamalizad, Richard Plettner, Chengzhi Pan, Nader Bagherzadeh. 3-6 [doi]
• Video transmission through domain specific reconfigurable architecurtes over short distance wireless medium utilizing Bluetooth IEEE 802.15.1™ standard [architecurtes read architectures]Imran Ahmed, Tughrul Arslan, Sami Khawam. 7-10 [doi]
• On-chip testing of embedded silicon transducersSalvador Mir, Benoît Charlot, Libor Rufer, Bernard Courtois. 13-18 [doi]
• Fast techniques for standby leakage reduction in MTCMOS circuitsWenxin Wang, Mohab Anis, Shawki Areibi. 21-24 [doi]
• Analysis and design of low-power multi-threshold MCMLHassan Hassan, Mohab Anis, Mohamed I. Elmasry. 25-29 [doi]
• A high-speed power and resolution adaptive flash analog-to-digital converterSunny Nahata, Kyusun Choi, Jincheol Yoo. 33-36 [doi]
• A background calibration scheme for pipelined ADCs including non-linear operational amplifier gain and reference error correctionAndreas Larsson, Sameer Sonkusale. 37-40 [doi]
• Analog-to-digital conversion for SONET OC-192Ayman H. Ismail, Mohamed I. Elmasry. 41-44 [doi]
• Parallel time interleaved delta sigma band pass analog to digital converter for SOC applicationsSaiyu Ren, Ray Siferd, Robert Blumgold. 45-48 [doi]
• Transparent SOC: on-chip analyzing techniques and implementation for embedded processorMakoto Saen, Motohiro Nakagawa, Junichi Nishimoto, Tomoyuki Kodama, Fumio Arakawa. 51-54 [doi]
• A circuit-switched network architecture for network-on-chipJian Liu, Li-Rong Zheng, Hannu Tenhunen. 55-58 [doi]
• Clock tree tuning using shortest paths polygonHaydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili. 59-62 [doi]
• Multilevel routing with jumper insertion for antenna avoidanceTsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen. 63-66 [doi]
• Signal integrity implications of inductor-to-circuit proximityRadu M. Secareanu, Qiang Li, Sushil Bharatan, Carl Kyono, Rainer Thoma, Mel Miller, Olin L. Hartin. 69-72 [doi]
• POMR: a power-optimal maze routing methodologyAhmed Youssef, Mohab Anis, Mohamed I. Elmasry. 73-77 [doi]
• Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distributionKaveh Shakeri, Muhannad S. Bakir, James D. Meindl. 78-81 [doi]
• Leakage aware SER reduction technique for UDSM logic circuitsPraveen Elakkumanan, Vishwanath Ananthakrishnan, Ashok Narasimhan, Ramalingam Sridhar. 82-85 [doi]
• A generic macromodel for coupling between inductors and interconnects for R.F.I.C. layoutsTejasvi Das, Ghanshyam Nayak, Ponnathpur R. Mukund. 89-92 [doi]
• 3-22GHz CMOS distributed single-balanced mixerXiaohua Fan, Edgar Sánchez-Sinencio. 93-96 [doi]
• Impact of technology scaling on RF CMOSHassan Hassan, Mohab Anis, Mohamed I. Elmasry. 97-101 [doi]
• Silencer!: a tool for substrate noise coupling analysisPatrick Birrer, Terri S. Fiez, Kartikeya Mayaram. 105-108 [doi]
• Adaptive response surface modeling-based method for analog circuit sizingDonghoon Han, Abhijit Chatterjee. 109-112 [doi]
• Circuit level modeling and simulation of mixed-technology systemsBo Wan, Pavel V. Nikitin, C.-J. Richard Shi. 113-116 [doi]
• Power-efficient implementation of turbo decoder in SDR systemByung-Tae Kang, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides. 119-122 [doi]
• A power-aware scalable pipelined Booth multiplierHanho Lee. 123-126 [doi]
• High throughput and low power FIR filtering IP coresC. H. Wang, Ahmet T. Erdogan, Tughrul Arslan. 127-130 [doi]
• Synthesis of SystemC models from SDF Ptolemy descriptionsBrian A. Jackson, James R. Armstrong. 133-134 [doi]
• A scalable and robust rail-to-rail delay cell for DLLsHåkan Bengtson, Christer Svensson. 135-136 [doi]
• FPGA implementation of efficient Kalman band-pass sigma-delta filter for application in FM demodulationCharoensak Charayaphan, Saman S. Abeysekera. 137-138 [doi]
• System-level design of low-cost FPGA hardware for real-time ICA-based blind source separationCharoensak Charayaphan, Farook Sattar. 139-140 [doi]
• A 0.13μm 1Gb/s/channel store-and-forward network on-chipFilippo Mondinelli, Michele Borgatti, Zsolt Miklós Kovács-Vajna. 141-142 [doi]
• A memory allocation and assignment method using multiway partitioningNam-Hoon Kim, Peter A. Beerel, Ralph Peng. 143-144 [doi]
• Low-power driven standard-cell placement based on a multilevel force-directed algorithmYu-Hsiung Huang, Mely Chen Chi. 145-146 [doi]
• Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility studyHenrik Fredriksson, Christer Svensson. 147-148 [doi]
• Bandgap yield loss due to dislocations on RFSiGe transceiver ICs: failure analysis, designRalph Oberhuber, Christoph Hechtl, Klaus Schimpf, Berthold Staufer. 149-150 [doi]
• A novel phase detector for PAM-4 clock recovery in high speed serial linksKahn Li Lim, Zeljko Zilic. 151-152 [doi]
• An efficient reformulation based architecture for adaptive forward error correction decoding in wireless applicationsYao Gang, Tughrul Arslan, Ahmet T. Erdogan. 153-154 [doi]
• A new level shifter in ultra deep sub-micron for low to wide range voltage applicationsKyoung-Hoi Koo, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim. 155-156 [doi]
• Design of a programmable cryptoprocessor for multiple cryptosystemsJeemyong Lee, Wooseok Kwon, Sanghun Lee, Chanho Lee. 157-158 [doi]
• Exploration of GFP frame delineation architectures for network processingCiaran Toal, Sakir Sezer. 159-162 [doi]
• Reducing crosstalk noise in high speed FPGAsArindam Mukherjee. 163-164 [doi]
• Coarse-grain reconfigurable XPP devices for adaptive high-end mobile video-processingJürgen Becker, Martin Vorbach. 165-166 [doi]
• Robust multi-phase clock generation with reduced jitterKalle Folkesson, Christer Svensson. 167-168 [doi]
• A low clock load conditional flip-flopMartin Hansson, Atila Alvandpour. 169-170 [doi]
• Crosstalk induced fault analysis in DRAMsZemo Yang, Samiha Mourad. 171-172 [doi]
• A synchronous interface for SoCs with multiple clock domainsVisvesh S. Sathe, Conrad H. Ziesler, Marios Papaefihymiou, Suhwan Kim, Stephen V. Kosonocky. 173-174 [doi]
• Achieving higher dynamic range in flash A/D convertersNikolas Stefanou, Sameer R. Sonkusale. 175-176 [doi]
• Low energy transmission coding for on-chip serial communicationsKangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. 177-178 [doi]
• Clock tree layout design for reduced delay uncertaintyDimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman. 179-180 [doi]
• A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assistGerard Boudon, Alan Wall, Joe Foster, Barry Wolford, John Fakiris. 183-186 [doi]
• An embedded read only memory architecture with a complementary and two interchangeable power/performance design pointsSteven Eustis. 187-190 [doi]
• A generic reconfigurable neural network architecture as a network on chipTheocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Vamsi Srikantam. 191-194 [doi]
• Application specific instruction memory transformations for power efficient, fault resilient embedded processorsRaid Ayoub, Peter Petrov, Alex Orailoglu. 195-198 [doi]
• Multi-processor SoC integration: a case study on BlueGene/LPascal Nsame, Yvon Savaria. 201-204 [doi]
• Communication on a segmented busTiberiu Seceleanu. 205-208 [doi]
• High speed mixed analog/digital PRML architecture for optical data storage systemMaxim Konakov, Jae-Wook Lee, Junghyun Lee, Eun-Jin Ryu, Eingseob Cho, Jungeun Lee, Hyunsu Chae, Jeongwon Lee. 209-212 [doi]
• A high-performance parallel mode EBCOT encoder architecture design for JPEG2000Yun Long, Chunhui Zhang, Fadi J. Kurdahi. 213-216 [doi]
• SRAM word-oriented redundancy methodology using built in self-repairJihyun Lee, Young-Jun Lee, Yong-Bin Kim. 219-222 [doi]
• On-chip network based embedded core testingJong-Sun Kim, Min-Su Hwang, Seungsu Roh, Ja Young Lee, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. 223-226 [doi]
• An efficient error-masking technique for improving the soft-error robustness of static CMOS circuitsSrivathsan Krishnamohan, Nihar R. Mahapatra. 227-230 [doi]
• Low-power on-chip bus architecture using dynamic relative delaysMaged Ghoneima, Yehea I. Ismail. 233-236 [doi]
• Battery-efficient task execution on portable reconfigurable computingBalasubramanian Sethuraman, Jawad Khan, Ranga Vemuri. 237-240 [doi]
• A leakage-tolerant low-leakage register file with conditional sleep transistorAmit Agarwal, Kaushik Roy, Ram K. Krishnamurthy. 241-244 [doi]
• MOS current mode logic: design, optimization, and variabilityHassan Hassan, Mohab Anis, Mohamed I. Elmasry. 247-250 [doi]
• A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decodersMichael Wieckowski, Martin Margala. 251-254 [doi]
• Simultaneous bidirectional PAM-4 link with built-in self-testMing-Ta Hsieh, Gerald E. Sobelman. 255-258 [doi]
• Retiming and clock scheduling to minimize simultaneous switchingArindam Mukherjee, Rajsaktish Sankaranarayan. 259-262 [doi]
• Network processors for access network (NP4AN): trends and challengesXiaoning Nie, Ulf Nordqvist, Lajos Gazsi, Dake Liu. 265-269 [doi]
• A weighted fair queuing finishing tag computation architecture and implementationColm McKillen, Sakir Sezer. 270-273 [doi]
• An asynchronous on-chip network router with quality-of-service (QoS) supportTomaz Feliciian, Stephen B. Furber. 274-277 [doi]
• An optically differential reconfigurable gate array using a 0.18 μm CMOS processMinoru Watanabe, Fuminori Kobayashi. 281-284 [doi]
• Rapid energy estimation of computations on FPGA based soft processorsJingzhao Ou, Viktor K. Prasanna. 285-288 [doi]
• A virtual channel router for on-chip networksNikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen. 289-293 [doi]
• An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signalingMarcus van Ierssel, Joyce Wong, Ali Sheikholeslami. 297-300 [doi]
• Substrate noise optimization in early floorplanning for mixed signal SOCsGrzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske. 301-304 [doi]
• A new multi-channel on-chip-bus architecture for system-on-chipsSanghun Lee, Chanho Lee, Hyuk-Jae Lee. 305-308 [doi]
• Analysis and design of monolithic, high PSR, linear regulators for SoC applicationsVishal Gupta, Gabriel A. Rincón-Mora, Prasun Raha. 311-315 [doi]
• High-gain high-speed operational amplifier in digital 120nm CMOSFranz Schlögl, Horst Dietrich, Horst Zimmermann. 316-319 [doi]
• A compensation technique for transistor mismatch in current mirrorsSripriya R. Bandi, Ponnathpur R. Mukund. 320-323 [doi]
• A new design for built-in self-test of 5GHz low noise amplifiersJee-Youl Ryu, Bruce C. Kim. 324-327 [doi]
• Decoupling capacitors for power distribution systems with multiple power supply voltagesMikhail Popovich, Eby G. Friedman. 331-334 [doi]
• Low power repeaters driving RC interconnects with delay and bandwidth constraintsGuoqing Chen, Eby G. Friedman. 335-339 [doi]
• Global interconnect optimization with simultaneous macrocell placement and repeater insertionYuantao Peng, Xun Liu. 340-343 [doi]
• Mutual inductance modeling for multiple RLC interconnects with application to shield insertionJunmou Zhang, Eby G. Friedman. 344-347 [doi]
• A novel half-rate architecture for high-speed clock and data recoveryQiurong He, Milton Feng. 351-354 [doi]
• SoC design of remote terminals for wireless telemetry systemWonjae Lee, Sangyun Hwang, Minho Kwon, Seongjoo Lee, Jaeseok Kim. 355-358 [doi]
• An improved delay-hopped transmitted-reference ultra wideband architectureXiaomin Chen, Sayfe Kiaei. 359-362 [doi]
• VLSI design and analysis of a critical-band processor for speech recognitionChao Wang, Yit-Chow Tong, Yu Shao. 365-368 [doi]
• An application-specific processor hard macro for real-time controlXiaofeng Wu, Vassilios A. Chouliaras, Roger Goodall. 369-372 [doi]
• FPGA-efficient phase-to-I/Q architectureIreneusz Janiszewski, Hermann Meuth, Bernhard Hoppe. 373-376 [doi]
• A 3.8Ghz channel-select filter using 0.18μm CMOSJiandong Ge, Anh Dinh. 379-382 [doi]
• Optimum design and trade-offs for a triple-band LNA for GSM, WCDMA and GPS applicationsNazanin Darbanian, Sayfe Kiaei, Shahin Farahani. 383-386 [doi]
• Extended dynamic voltage scaling for low power designBo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner. 389-394 [doi]
• ChipPower: an architecture-level leakage simulatorYuh-Fang Tsai, Ananth Hegde Ankadi, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides. 395-398 [doi]
• CoolPression - a hybrid significance compression technique for reducing energy in cachesMrinmoy Ghosh, Weidong Shi, Hsien-Hsin S. Lee. 399-402 [doi]