Table of Contents

• T1A: Time sensitive networks for industry 4.0Thomas Leyrer. 1 [doi]
• T2A: Analog and RF circuitsM. B. Srinivas. 1 [doi]
• F2A: Low power designEduardo Wächter. 1 [doi]
• T1B: Special session: Data analytics driven design for yield, manufacturability and reliability: Where machine learning meets design automationJohanna Sepúlveda. 1 [doi]
• Technical program overviewHelen Li. 1 [doi]
• F2B: On-chip fabricsChung-Ta King. 1 [doi]
• Opening remarksJürgen Becker. 1 [doi]
• T2B: Machine learning and parallel architecturesThorsten Lorenzen. 1 [doi]
• The triangle of power density, circuit degradation and reliabilityJörg Henkel. 1-2 [doi]
• W3A: Design of reconfigurable and multiprocessor systemsTolga Soyata. 1 [doi]
• IBM Q - Introduction into quantum computing with live demoAlbert Frisch. 1-2 [doi]
• Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technologyHarsh Rawat, K. Bharath, Alexander Fell. 1-6 [doi]
• Propelling breakthrough embedded microprocessors by means of integrated photonicsDavide Bertozzi, Sébastien Rumley. 1-3 [doi]
• Time sensitive networks for industry 4.0Thomas Leyrer. 1-2 [doi]
• W2B: Design methodologies for SoCsVivek Nautiyal. 1 [doi]
• Wednesday keynote II: Advanced technology for automotive cockpits, industrial human-machine-interface and IoT systems - Optimization of technology - Architecture - DesignRon Martino. 1-3 [doi]
• Reliability for IoT and automotive marketsSubhadeep Ghosh, Scott Martin, Shane Stelmach. 1-3 [doi]
• The path to global connectivity - Wireless communication enters the next generationJosef Hausner. 1-2 [doi]
• The triangle of power density, circuit degradation and reliabilityJörg Henkel. 1 [doi]
• Low power circuit optimization for IoTMichael Pronath. 1-2 [doi]
• Design automation for Labs-on-Chip: A new "playground" for SoC designersRobert Wille, Bing Li. 1-2 [doi]
• FDSOI design experience and recommendationsHerbert Preuthen, Jurgen Dirks. 1-2 [doi]
• W1A: MemoriesHai Helen Li. 1 [doi]
• Wednesday keynote I: FDSOI and FINFET for SoC developmentsGerd Teepe. 1-2 [doi]
• W1B: Application specific designsAmlan Ganguly. 1 [doi]
• F1A: Networks on chipMostafa Khamis. 1 [doi]
• The memory challenge in computing systems: A surveyNorbert Wehn. 1 [doi]
• The memory challenge in computing systems: A surveyNorbert Wehn. 1-2 [doi]
• Panel discussion: Autonomy, technology, safety - Where will automotive electronics go in the next decade?Mircea Stan. 1 [doi]
• Opening remarksJürgen Becker. 1 [doi]
• F1B: Algorithms, models and simulation for systemsBei Yu. 1 [doi]
• The importance of benchmarking for charge-based and beyond CMOS devicesAndrew Marshall, Nishtha Sharma. 1-2 [doi]
• W3B: Special session: Secure multi-processors systems-on-chip for critical applicationsBing Li. 1 [doi]
• W2A: Analog-to-digital converters and low-noise amplifiersChing-Yuan Yang. 1 [doi]
• A random access analog memory with master-slave structure for implementing hexadecimal logicRenyuan Zhang, Mineo Kaneko. 7-11 [doi]
• An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processorsVivek Nautiyal, Gaurav Singla, Lalit Gupta, Sagar Dwivedi, Martin Kinkade. 12-17 [doi]
• A 590MDE/s semi-global matching processor with lossless data compressionKyeongryeol Bong, Kyuho Jason Lee, Hoi-Jun Yoo. 18-22 [doi]
• Secure digital communication based on Lorenz stream cipherAhmed S. Alshammari, Mohamed I Sobhy, Peter Lee. 23-28 [doi]
• BlooXY: On a non-invasive blood monitor for the IoT contextDaniel Florez, Johanna Sepúlveda. 29-34 [doi]
• A low-pass continuous-time delta-sigma interface circuit for wideband MEMS gyroscope readout ASICYoungtae Yang, Jaehoon Jun, Suhwan Kim. 35-39 [doi]
• A 13.5 bit 1.6 mW 3rd order CT ΣΔ ADC for integrated capacitance sensor interfaceJaved S. Gaggatur, Gaurab Banerjee. 40-44 [doi]
• A low power, programmable 12-bit two step SAR-flash ADC for signal processing applicationsMahesh Kumar Adimulam, Krishna Kumar Movva, M. B. Srinivas. 45-50 [doi]
• Low-noise high input impedance 8-channels chopper-stabilized EEG acquisition systemZhengnan Yan, Mohamed Atef, Guoxing Wang, Yong Lian. 51-55 [doi]
• Pin accessibility evaluating model for improving routability of VLSI designsHong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera. 56-61 [doi]
• Hybrid multi-swarm optimization based NoC synthesisMuhammad Obaidullah, Gul N. Khan. 62-67 [doi]
• Multifractal on-chip traffic generation under TLMJose Eduardo Chiarelli Bueno Filho, Wang Jiang Chau. 68-73 [doi]
• Automated, inter-macro channel space adjustment and optimization for faster design closurePraveen Kumar, Alexander Fell, Sachin Mathur. 74-79 [doi]
• Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chainTakashi Imagawa, Koki Honda, Hiroyuki Ochi. 80-85 [doi]
• Robust throughput boosting for low latency dynamic partial reconfigurationAlberto Nannarelli, Marco Re, Gian-Carlo Cardarilli, Luca Di Nunzio, M. Spaziani Brunella, Rocco Fazzolari, F. Carbonari. 86-90 [doi]
• Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate arrayTakumi Fujimori, Minoru Watanabe. 91-95 [doi]
• A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfigurationMarco Pagani, Alessio Balsini, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo. 96-101 [doi]
• Introduction to hardware-oriented security for MPSoCsIlia Polian, Francesco Regazzoni, Johanna Sepúlveda. 102-107 [doi]
• On the security evaluation of the ARM TrustZone extension in a heterogeneous SoCEl Mehdi Benhani, Cédric Marchand 0002, Alain Aubert, Lilian Bossuet. 108-113 [doi]
• Securing FPGA SoC configurations independent of their manufacturersNisha Jacob, Jakob Wittmann, Johann Heyszl, Robert Hesselbarth, Florian Wilde, Michael Pehl, Georg Sigl, Kai Fischer. 114-119 [doi]
• Cache attacks and countermeasures for NTRUEncrypt on MPSoCs: Post-quantum resistance for the IoTJohanna Sepúlveda, Andreas Zankl, Oliver Mischke. 120-125 [doi]
• A 0.13 CMOS integrated circuit for electrical impedance spectroscopy from 1 kHz to 10 GHzRonny Garcia-Ramirez, Alfonso Chacon-Rodriguez, Renato Rimolo-Donadio. 126-131 [doi]
• A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnectsSuryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark Indovina, Amlan Ganguly. 132-137 [doi]
• A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCsDongjoo Shin, Youchang Kim, Hoi-Jun Yoo. 138-142 [doi]
• A CMOS third order ΔΣ modulator with inverter-based integratorsJeong H. Choi, Kwang S. Yoon. 143-148 [doi]
• A novel power reduction technique using wire multiplexingMostafa Said, Hossam Hassan, Hyungwon Kim, Mostafa Khamis. 149-152 [doi]
• Auto-SI: An adaptive reconfigurable processor with run-time loop detection and accelerationTanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker. 153-158 [doi]
• CNN inference: VLSI architecture for convolution layer for 1.2 TOPSMihir N. Mody, Manu Mathew, Shyam Jagannathan, Arthur Redfern, Jason Jones, Thorsten Lorenzen. 158-162 [doi]
• Digital spiking neuron cells for real-time reconfigurable learning networksHaipeng Lin, Amir Zjajo, Rene van Leuken. 163-168 [doi]
• Efficient virtual channel allocator for NoC router micro-architectureYun Long Lan, V. Muthukumar. 169-174 [doi]
• Investigation of diode triggered silicon control rectifier turn-on time during ESD eventsAhmed Y. Ginawi, Robert Gauthier, Tian Xia. 175-178 [doi]
• Magneto-electric magnetic tunnel junction based analog circuit optionsNishtha Sharma 0001, Jonathan Bird, Peter Dowben, Andrew Marshall. 179-183 [doi]
• Optimizing the heterogeneous network on-chip design in manycore architecturesTung Thanh Le, Rui Ning, Dan Zhao, Hongyi Wu, Magdy Bayoumi. 184-189 [doi]
• Power and area evaluation of a fault-tolerant network-on-chipThawra Kadeed, Eberle A. Rambo, Rolf Ernst. 190-195 [doi]
• Selectable grained reconfigurable architecture (SGRA) and its design automationRyosuke Koike, Takashi Imagawa, Roberto Yusi Omaki, Hiroyuki Ochi. 196-201 [doi]
• Thermal simulation aided 98mJ integrated high side and low side drivers design for safety SOCsSri Navaneeth Easwaran, Samir Camdzic, Robert Weigel. 202-205 [doi]
• Virtual white board: Leveraging investments in interface based design and executable specificationTodd Hiers, Chunhua Hu, Brian Karguth, Chuck Fuoco. 206-210 [doi]
• Realization of buck converter with adaptive variable-frequency controlChing-Yuan Yang, Jen-Yan Huang, Jun-Hong Weng. 211-214 [doi]
• Supercapacitor-based embedded hybrid solar/wind harvesting system architecturesMohamadhadi Habibzadeh, Moeen Hassanalieragh, Tolga Soyata, Gaurav Sharma. 215-220 [doi]
• MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devicesLucie Broyde, Kent W. Nixon, Xiang Chen, Hai Li, Yiran Chen. 221-226 [doi]
• Accelerating chip design with machine learning: From pre-silicon to post-siliconCheng Zhuo, Bei Yu, Di Gao. 227-232 [doi]
• Lithography hotspot detection: From shallow to deep learningHaoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young. 233-238 [doi]
• Generative adversarial network based scalable on-chip noise sensor placementJinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi. 239-242 [doi]
• Application of machine learning methods in post-silicon yield improvementBaris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann. 243-248 [doi]
• A constant bandwidth switched-capacitor programmable-gain amplifier utilizing adaptive miller compensation techniqueHyunjong Kim, Yujin Park, Han Yang, Suhwan Kim. 249-252 [doi]
• Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOSJan Pliva, Mahdi Khafaji, László Szilágyi, Ronny Henker, Frank Ellinger. 253-257 [doi]
• A 2.4-GHz dual-mode resizing power amplifier with a constant conductance output matchingWei-Lun Ou, Yu-Kai Tsai, Po-Yen Tseng, Liang-Hung Lu. 258-261 [doi]
• A low complexity UWB PHY baseband transceiver for IEEE 802.15.6 WBANAtef H. Bondok, Awny M. El-Mohandes, Ahmed Shalaby, Mohammed S. Sayed. 262-267 [doi]
• FPGA-based CNN inference accelerator synthesized from multi-threaded C softwareJin-Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason Helge Anderson. 268-273 [doi]
• Designing bio-inspired autonomous error-tolerant massively parallel computing architecturesLizheng Liu, Yi Jin, Yi Liu, Ning Ma, Zhuo Zou, Lirong Zheng. 274-279 [doi]
• LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural networkHantao Huang, Leibin Ni, Hao Yu. 280-285 [doi]
• Region based cache coherence for tiled MPSoCsAkshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf. 286-291 [doi]
• Providing throughput guarantees in mixed-criticality networks-on-chipSebastian Tobuschat, Rolf Ernst. 292-297 [doi]
• System-level simulator for process variation influenced synchronous and asynchronous NoCsSayed Taha Muhammad, Ali A. El-Moursy, Magdy A. El-Moursy, Hesham F. A. Hamed. 298-303 [doi]
• Fairness-oriented switch allocation for networks-on-chipZicong Wang, Xiaowen Chen, Chen Li 0015, Yang Guo. 304-309 [doi]
• Router-level performance driven dynamic management in hierarchical networks-on-chipMingmin Bai, Dan Zhao, Magdy A. Bayoumi. 310-315 [doi]
• Application specific component-service-aware trace generation on Android-QEMUHao-Lun Wei, Chung-Ta King, Bhaskar Das, Mei-Chiao Peng, Chen-Chieh Wang, Hsun-Lun Huang, Juin-Ming Lu. 316-321 [doi]
• A unified HW/SW system-level simulation framework for next generation wireless systemNana Sutisna, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi. 322-327 [doi]
• A graph based synthesis procedure for linear analog functionMousumi Bhanja, Baidyanath Ray. 328-333 [doi]
• A study on the energy-precision tradeoffs on commercially available processors and SoCs with an EPI based energy modelJeremy Schlachter, Mike Fagan, Krishna V. Palem, Christian Enz. 334-339 [doi]
• Approximate compressed sensing for hardware-efficient image compressionSai Praveen Kadiyala, Vikram Kumar Pudi, Siew Kei Lam. 340-345 [doi]
• Content-aware line-based power modeling methodology for image signal processorChun-Wei Chen, Ming-Der Shieh, Juin-Ming Lu, Hsun-Lun Huang, Yao-Hua Chen. 346-350 [doi]
• A multi-format floating-point multiplier for power-efficient operationsAlberto Nannarelli. 351-356 [doi]
• Energy-efficient wireless interconnection framework for multichip systems with in-package memory stacksMd Shahriar Shamim, M. Meraj Ahmed, Naseef Mansoor, Amlan Ganguly. 357-362 [doi]
• System management recovery protocol for MPSoCsVinicius Fochi, Luciano L. Caimi, Marcelo Ruaro, Eduardo Wächter, Fernando Gehm Moraes. 367-374 [doi]
• Haar-based interconnect coding for energy effective medium/long range data transportNicoleta Cucu Laurenciu, Sorin Dan Cotofana. 375-380 [doi]
• A decomposition-based system level synthesis method for heterogeneous multiprocessor architecturesGyorgy Racz, Péter Arató. 381-386 [doi]