VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers - researchr publication

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Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd M. Austin, Ricardo Reis, editors, VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018, Revised and Extended Selected Papers. Volume 561 of IFIP Advances in Information and Communication Technology, Springer, 2019. [doi]

Conference: vlsi2019

Abstract is missing.

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA LoadNaoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada. 1-13 [doi]

An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT CommunicationShahzad Muzaffar, Ibrahim Abe M. Elfadel. 14-31 [doi]

The Connection Layout in a Lattice of Four-Terminal SwitchesAnna Bernasconi 0001, Antonio Boffa, Fabrizio Luccio, Linda Pagli. 32-52 [doi]

Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLSLuca Stornaiuolo, Marco Rabozzi, Marco D. Santambrogio, Donatella Sciuto, Catalin Bogdan Ciobanu, Giulio Stramondo, Ana Lucia Varbanescu. 53-78 [doi]

Rectification of Arithmetic Circuits with Craig Interpolants in Finite FieldsUtkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu. 79-106 [doi]

Energy-Accuracy Scalable Deep Convolutional Neural Networks: A Pareto AnalysisValentino Peluso, Andrea Calimera. 107-127 [doi]

ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH CodeSwagata Mandal, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay. 128-146 [doi]

Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing SystemsMd. Adnan Zaman, Rajeev Joshi, Srinivas Katkoori. 147-166 [doi]

Mapping Spiking Neural Networks on Multi-core Neuromorphic Platforms: Problem Formulation and Performance AnalysisFrancesco Barchi, Gianvito Urgese, Enrico Macii, Andrea Acquaviva. 167-186 [doi]

Improved Test Solutions for COTS-Based Systems in Space ApplicationsRiccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez 0001, Matteo Sonza Reorda, Jan-Gerd Mess. 187-206 [doi]

Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their DetectionVíctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy. 207-231 [doi]

Assessment of Low-Budget Targeted Cyberattacks Against Power SystemsXiaorui Liu, Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos. 232-256 [doi]

Efficient Hardware/Software Co-design for NTRUTim Fritzmann, Thomas Schamberger, Christoph Frisch, Konstantin Braun, Georg Maringer, Johanna Sepúlveda. 257-280 [doi]

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