Table of Contents

• Invited Address: The InfoPad Project: Review and Lessons LearnedRobert W. Brodersen. 2-3
• Invited Address: A Wireless Portable Video-On-Demand SystemTeresa H. Y. Meng. 4
• Algorithmic and Architectural Transformations for Low Power Realization of FIR FiltersMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. 12-17 [doi]
• Coding for Low-Power Address and Data Busses: A Source-Coding Framework and ApplicationsSumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj. 18-23
• A Power Management Methodology for High-Level SynthesisGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey. 24-19
• Freedom: Statistical Behavioral Estimation of System Energy and PowerSuhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar. 30-36 [doi]
• Extensions to Programmable DSP architectures for Reduced Power DissipationMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. 37 [doi]
• Embedded Tutorial: Layout Driven Synthesis or Synthesis Driven LayoutNaveed A. Sherwani, Prashant Sawkar. 44-47
• Top-Down Approach to Technology Migration for Full-Custom Mask LayoutsZ. V. Apanovich, Alexander G. Marchuk. 48-52 [doi]
• Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing ConsiderationsBharat Krishna, C. Y. Roger Chen, Naresh Sehgal. 53-58
• Partitioning VLSI Floorplans by Staircase Channels for Global RoutingSubhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya. 59-64 [doi]
• Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal ModelSandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya. 65 [doi]
• Invited Paper: Broadband U-NII Wireless DataNeil Weste, David J. Skellern, Terry Percival. 72-77
• A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDLBengt Svantesson, Shashi Kumar, Ahmed Hemani. 78-84
• Interface Synthesis for Embedded Applications in a Co Design EnvironmentAnupam Basu, Raj S. Mitra, Peter Marwedel. 85-90 [doi]
• Hardware/Software Co-design of a High-end Mixed Signal MicrocontrollerPradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta. 91-96 [doi]
• Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW CodesignSandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee. 97
• mproving Area Efficiency of FIR Filters Implemented Using Distributed ArithmeticAmit Sinha, Mahesh Mehendale. 104-109 [doi]
• Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR FiltersMahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh. 110-115 [doi]
• An Embedded Processor for Integrated Navigation ReceiverAnteneh Alemu Abbo. 116-121 [doi]
• A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech SignalAnsgar Drolshagen, Walter Anheier, C. Chandra Sekhar. 122-127 [doi]
• Arbitrary Precision Arithmetic - SIMD StyleS. Balakrishnan, Soumitra Kumar Nandy. 128-132 [doi]
• Improving Concurrency for Cosine-modulated Filterbank WindowingC. G. Hiremath, Sriram Jayasimha. 133 [doi]
• A Low Power Video Frequency Continuous Time FilterSrinivasan Venkatraman, Srikanth Natarajan, K. Radhakrishna Rao. 140-144 [doi]
• A Technique to Improve Capture Range of a PLL in PRML Read ChannelC. Srinivasan. 145-149
• A New Tuning Scheme for Continuous Time FiltersSrinivasan Venkatraman, Srikanth Natarajan, K. Radhakrishna Rao. 150-154 [doi]
• Design and VLSI Implementation of an Adaptive Delta-Sigma ModulatorGert Cauwenberghs. 155-160 [doi]
• A Novel Translinear Principle Based BiMOS TransconductorS. Pradeep Kiran, K. Radhakrishna Rao. 161-166
• Symbolic Analysis of Analog Integrated CircuitsC. F. Prince, Vinita Vasudevan. 167 [doi]
• Partial Scan Selection Based on Dynamic Reachability and Observability InformationMichael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel. 174-180 [doi]
• Peripheral Partitioning and Tree Decomposition for Partial ScanArun Balakrishnan, Srimat T. Chakradhar. 181-186 [doi]
• Synthesis of Testable RTL DesignsC. P. Ravikumar, Sumit Gupta, Akshay Jajoo. 187-192
• Controller Resynthesis for Testability Enhancement of RTL Controller/Data path CircuitsSrivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey. 193-198 [doi]
• Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential CircuitsHuy Nguyen, Rabindra K. Roy, Abhijit Chatterjee. 199-204
• Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay FaultsDebesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya. 205 [doi]
• Partitioning sequential circuits for low powerSumit Roy, Prithviraj Banerjee, Majid Sarrafzadeh. 212-217 [doi]
• Optimizing Logic Design Using Boolean TransformsPramit Chavda, James Jacob, Vishwani D. Agrawal. 218-221 [doi]
• Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence CheckingAarti Gupta, Pranav Ashar. 222-225 [doi]
• False Path Detection at Transistor LevelAbhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. N. Nandakumar. 226-229
• Computation of Lower and Upper Bounds for Switching Activity: A Unified ApproachVamsi Krishna, Ramamurti Chandramouli, N. Ranganathan. 230-233
• Timing Driven Multi-FPGA Board PartitioningRaghu Burra, Dinesh Bhatia. 234 [doi]
• Design of a Measurement and Interface Integrated Circuit for Characterization of Switched Current Memory CellsAdriano M. Pereira, Tales Cleber Pimenta, Robson L. Moreno, Edgar Charry R., Alberto M. Jorge. 240-243 [doi]
• Current Mode Ternary D/A ConverterSaeid Nooshabadi, G. S. Visweswaran, D. Nagchoudhuri. 244-248
• A Modified Line Expansion Algorithm for Device-level Routing of Analog CircuitsPrakash Gopalakrishnan, Vinita Vasudevan. 249-252 [doi]
• Constraint Allocation in Analog System SynthesisNagu R. Dhanwada, Ranga Vemuri. 253-258 [doi]
• Novel Memory Bus Driver/Receiver Architecture for Higher ThroughputGregory E. Beers, Lizy Kurian John. 259-264 [doi]
• Incremental Autojogging using Range SpacesCyrus Bamji, Ravi Varadarajan. 265 [doi]
• Automatic Test Pattern Generation for Sequential Circuits Using Genetic AlgorithmsV. Rajesh, Ajai Jain. 270-273 [doi]
• Impact and Cost of Modeling Memories for ATPG for Partial Scan DesignsSitaram Yadavalli, Sanjay Sengupta. 274-278
• On Test Compaction Objectives for Combinational and Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 279-284 [doi]
• Mixed-Signal TestAnanta K. Majhi, Vishwani D. Agrawal. 285-288 [doi]
• A Method for Synchronizing IEEE 1149.1 Test Access Port for Chip Level Testability AccessDilip Bhavsar. 289-292
• Hybrid Testing Schemes Based on Mutual and Signature TestingMohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar. 293
• Keynote Address: The Networked Society - Enabled by DSP SolutionsPallab K. Chatterjee. 298
• Invited Address: Hybrid Reconfigurable Processors - The Road to Low-Power ConsumptionJan M. Rabaey. 300-303
• Invited Address: Integrated Memory/Logic Architecture for Image ProcessingCharles Sodini, Jeffrey C. Gealow, Zubair A. Talib, Ichiro Masaki. 304
• Evolution of Architectural Concepts and Design Methods of MicroprocessorsS. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, A. Karmakar, Chandra Shekhar, Sudhir Kumar, Amit K. Agarwal. 312-317 [doi]
• A Framework for a Parallel Architecture Dedicated to Soft ComputingGiuseppe Ascia, Vincenzo Catania. 318-321 [doi]
• Fast Arithmetic on Xilinx 5200 FPGABernard Laurent, G. Bosco, Gabriele Saucier. 322-325 [doi]
• VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead DelayS. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, M. S. Diamondstein. 326-329 [doi]
• A Low Power Floating Point AccumulatorR. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili. 330 [doi]
• Simulation and Synthesis of VLSI Communication SystemsRajeev Jain, Charles Chien, Etan G. Cohen, Leader Ho. 336-341 [doi]
• CFSMcharts: A New Language for Microprocessor Based system DesignPartha S. Roop, Arcot Sowmya. 342-346 [doi]
• COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System ArchitecturesBharat P. Dave, Niraj K. Jha. 347-354 [doi]
• An Object-Oriented Concept for Intelligent Library FunctionsJohnny Öberg, Axel Jantsch, Anshul Kumar. 355-358 [doi]
• An Evolutionary Approach to System RedesignDong-Hyun Heo, Alice C. Parker, C. P. Ravikumar. 359 [doi]
• Tutorial: Delay Fault Models and CoverageAnanta K. Majhi, Vishwani D. Agrawal. 364-369 [doi]
• Testability Preserving and Enhancing Transformations for Robust Delay Fault TestabilitAmey Karkare, Manoj Singla, Ajai Jain. 370-373 [doi]
• Automated AC (Timing) Characterization for Digital Circuit TestingS. Balajee, Ananta K. Majhi. 374-377 [doi]
• Computing Stress Tests for Gate Oxide ShortsVinay Dabholkar, Sreejit Chakravarty. 378-391 [doi]
• A Stochastic Method for Defect Level Analysis of Pseudorandom TestingWen-Ben Jone, Sunil R. Das. 382 [doi]
• Decomposition Strategies and their Performance in Fpga-Based Technology MappingHenry Selvaraj, Miroslawa Nowicka, Tadeusz Luba. 388-393 [doi]
• A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGAM. Bhaskar Sherigar, A. S. Mahadevan, K. Senthil Kumar, Sumam David. 394-399
• Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function LibrarySitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar. 400-405
• New Net Models for Spectral Netlist PartitioningP. S. Nagendra Rao, C. S. Jayathirtha, C. S. Raghavendra Prasad. 406 [doi]
• A Low Voltage Mixed Signal ASIC for Digital Clinical ThermometerAtul Wokhlu, R. Venkat Krishna, Sandeep Agarwal. 412 [doi]
• A VLSI ATM Switch Architecture for VBR TrafficNagarajan Ranganathan, Rajat Anand, Girish Chiruvolu. 420-427
• Simultaneous Scheduling, Binding and Floorplanning in High-level SynthesisPradeep Prabhakaran, Prithviraj Banerjee. 428-434 [doi]
• A Retiming Based Relaxation Heuristic for Resource-Constrained Loop PipeliningVinoo Srinivasan, Ranga Vemuri. 435-441 [doi]
• A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis TasksZhang Yang, Rajesh K. Gupta. 442-448 [doi]
• Web-based Distributed VLSI DesignDebashis Saha, Anantha Chandrakasan. 449 [doi]
• MIX: A Test Generation System for Synchronous Sequential CircuitsXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy. 456-463 [doi]
• On Test Pattern Compaction Using Random Pattern Fault SimulationSeiji Kajihara, Kewal K. Saluja. 464-469 [doi]
• Path Delay Testing: Variable-Clock Versus Rated-ClockSubhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal. 470-475 [doi]
• Diagnostic Simulation of Sequential Circuits Using Fault SamplingSrikanth Venkataraman, W. Kent Fuchs, Janak H. Patel. 476-481 [doi]
• Distributed Logic Simulation Algorithm using Preemption of Inconsistent EventsC. S. Raghu, S. Sundaram. 482 [doi]
• A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron ApplicationsTony Tsang. 490-494 [doi]
• Double Pass Transistor Logic for High Performance Wave Pipeline CircuitsRajesh S. Parthasarathy, Ramalingam Sridhar. 495-500 [doi]
• Circuit Design using Resonant Tunneling DiodesPinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González. 501-506 [doi]
• A New Statistical Approach to Timing Analysis of VLSI CircuitsRung-Bin Lin, Meng-Chiou Wu. 507 [doi]
• Finite State Machines: A Deeper Look into Synthesis Optimization for VHDLVijay A. Nebhrajani, Nayan Suthar. 516-521
• Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine SynthesisSantanu Chattopadhyay, Parimal Pal Chaudhuri. 522-527
• A Fast Two-level Logic MinimizerP. Srinivasa Rao, James Jacob. 528-533 [doi]
• An Improved Cost Heuristic for Transistor SizingCyrus Bamji, Manjit Borah. 534
• Efficient Verification and Synthesis using Design CommonalitiesGitanjali Swamy, Stephen A. Edwards, Robert K. Brayton. 542-551 [doi]
• Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch DesignSreeranga P. Rajan, Masahiro Fujita. 552-557 [doi]
• On-Chip Signature Checking for Embedded MemoriesMohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar. 558-563
• Efficient Signatures with Linear Space Complexity for Detecting Boolean Function EquivalenceSantanu Chattopadhyay, Parimal Pal Chaudhuri. 564
• Invited Address: Future Systems-on-a-Chip: Impact on Engineering EducationHugo De Man. 572-577
• Panel: Challenges for Future Systems on a ChipRajeev Jain. 578