Table of Contents

• Tutorial T1: Designing Secure SoCsSrivaths Ravi, Stefan Mangard. 3 [doi]
• Tutorial T2: Organic Electronics: Technology, Devices, Circuits, and ApplicationsS. Sundar Kumar Iyer, Vivek Subramanian. 4 [doi]
• Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and SmallerSubhomoy Chattopadhyay, Rakesh Patel. 5 [doi]
• Tutorial T4A: Formal Verification Techniques and Tools for Complex DesignsJacob A. Abraham, Daniel G. Saab. 6 [doi]
• Tutorial T4B: Formal Assertion-Based Verification in Industrial SettingPraveen Tiwari, Raj S. Mitra, Manu Chopra, Alok Jain. 7 [doi]
• Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and TrendsNikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha. 8 [doi]
• Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process VariationsSarma B. K. Vrudhula, Sarvesh Bhardwaj. 9 [doi]
• Tutorial T7A: Advanced IC PackagingEric Beyne. 10 [doi]
• Tutorial T7B: RF Analysis and Simulation with Focus on RF SiP MethodologySanjay Gupta, Taranjit Kukal, Alok Tripathi, Raja Mitra, Ashish Patni, Siddarth Shetty. 11 [doi]
• Tutorial T8A: Automated Application Engine Synthesis from C AlgorithmsVinod Kathail, Shail Aditya, Craig Gleason, Nagesh Chatekar. 12 [doi]
• Tutorial T8B: Performance Debugging of Complex Embedded SystemsSamarjit Chakraborty, Abhik Roychoudhury. 13 [doi]
• Tutorial IND1A: NeXperia - A Versatile Configurable Platform for Home and Mobile ComputingPuranjoy Bhattacharya. 14 [doi]
• Tutorial IND1B: Realtime Operating Systems for Embedded Systems DevelopmentUma Maheswar Rao, Suneel Sinha, Naveen Shenoy. 15 [doi]
• Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGAParimal Patel. 16 [doi]
• Tutorial IND2B: Structured Embedded Configuration and TestC. J. Clark. 17 [doi]
• Creating a Culture of InnovationWim Roelandts. 21-22 [doi]
• Scaling, Power and the Future of CMOSMark Horowitz. 23 [doi]
• Nanoelectronics Device Technologies: CMOS, Beyond and the Mysterious Case of Ockham s RazorSandip Tiwari. 24-25 [doi]
• Where Analog meets Digital and BeyondAhmad Bahai. 26 [doi]
• Concurrent Optimization of Technology and Design for Nano CMOSAjith Amerasekera. 27 [doi]
• Reasoning about the Trends and Challenges of Engineering Design AutomationAlberto L. Sangiovanni-Vincentelli. 28-30 [doi]
• Nexperia Computing Architecture for Connected Consumer ApplicationsJ. Augusto de Oliveira. 31 [doi]
• Convergence of Nanoelectronics and Living Cells: A New Frontier for Diagnostics and Therapy?Roberto Guerrieri. 32 [doi]
• Systems, Nano-technology and SiPRene Penning de Vries. 33 [doi]
• Extracting Logic Circuit Structure from Conjunctive Normal Form DescriptionsZhaohui Fu, Sharad Malik. 37-42 [doi]
• Efficient Microprocessor Verification using Antecedent Conditioned SlicingShobha Vasudevan, Vinod Viswanath, Jacob A. Abraham. 43-49 [doi]
• Synthesizing Verification Aware Models: Why and How?Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi. 50-56 [doi]
• Simulation Based Verification using Temporally Attributed Boolean LogicS. K. Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar. 57-62 [doi]
• Explicit Safety Property Strengthening in SAT-based InductionVishnu C. Vimjam, Michael S. Hsiao. 63-68 [doi]
• Reusing Learned Information in SAT-based ATPGGörschwin Fey, Tim Warode, Rolf Drechsler. 69-76 [doi]
• A Process Scheduler-Based Approach to NoC Power ManagementFeihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, R. Ramanarayanan, Balaji Vaidyanathan. 77-82 [doi]
• Analysis of RealTime Embedded Applications in the Presence of a Stochastic Fault ModelRanjani Sridharan, Rabi N. Mahapatra. 83-88 [doi]
• Online Dynamic Voltage Scaling using Task Graph Mapping Analysis for MultiprocessorsPravanjan Choudhury, P. P. Chakrabarti, Rajeev Kumar. 89-94 [doi]
• A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability AnalysisSayak Ray, Pallab Dasgupta, P. P. Chakrabarti. 95-102 [doi]
• Architecting Microprocessor Components in 3D Design SpaceBalaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. 103-108 [doi]
• Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI CircuitsSanghoan Chang, Gwan Choi. 109-114 [doi]
• FPGA Implementation of Low Power Parallel MultiplierSanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, R. M. Patrikar. 115-120 [doi]
• Architecture for Variable-Length Combined FFT, DCT, and MWT Transform Hardware for a Multi-ModeWireless SystemRohit Pandey, Michael L. Bushnell. 121-126 [doi]
• Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor BusesSharath Jayaprakash, Nihar R. Mahapatra. 127-134 [doi]
• Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless ReceiverR. Bagheri, A. Mirzaei, S. Chehrazi, A. A. Abidi. 135-140 [doi]
• A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLLVijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin Mishra, Abhijit Abhyankar. 141-145 [doi]
• A 2 GHz Low Power Down-conversion Quadrature Mixer in 0.18-µm CMOSShaikh K. Alam. 146-154 [doi]
• A Low Power Frequency Multiplication Technique for ZigBee TranscieverJagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur. 150-155 [doi]
• 7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency SynthesizerDebashis Mandal, T. K. Bhattacharyya. 156-164 [doi]
• Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking ModelFeng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan. 165-170 [doi]
• Design of Two-Stage Miller-Compensated Amplifiers Based on an Optimized Settling ModelHamed Aminzadeh, Mohammad Danaie, Reza Lotfi. 171-176 [doi]
• A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET ModelingYogesh Singh Chauhan, Francois Krummenacher, Renaud Gillon, Benoit Bakeroot, Michel J. Declercq, Adrian M. Ionescu. 177-182 [doi]
• Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-DesignDeblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta. 183-188 [doi]
• Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit SimulationM. Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal. 189-194 [doi]
• Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS PerspectiveElias Kougianos, Saraju P. Mohanty. 195-200 [doi]
• Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit SynthesisHuiying Yang, Ranga Vemuri. 201-206 [doi]
• Modeling and Analysis of Noise Margin in SET LogicChaitanya Sathe, Santanu Mahapatra. 207-214 [doi]
• A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded MicroprocessorsSoumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan. 215-220 [doi]
• Compiler-Directed Code Restructuring for Operating with Compressed ArraysTaylan Yemliha, Guangyu Chen, Ozcan Ozturk, Mahmut T. Kandemir, Vijay Degalahal. 221-226 [doi]
• Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data MappingsMahmut T. Kandemir, Ozcan Ozturk, Vijay Degalahal. 227-232 [doi]
• Power Reduction in VLIW Processor with Compiler Driven Bypass NetworkNeeraj Goel, Anshul Kumar, Preeti Ranjan Panda. 233-238 [doi]
• Customization of Register File Banking Architecture for Low PowerRakesh Nalluri, Rohan Garg, Preeti Ranjan Panda. 239-244 [doi]
• AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level ProgramsSameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Madhav P. Desai. 245-250 [doi]
• Locality-Aware Distributed Loop Scheduling for Chip MultiprocessorsLiping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, R. Ramanarayanan, Balaji Vaidyanathan. 251-258 [doi]
• Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental AttributesAshish Dobhal, Vishal Khandelwal, Ankur Srivastava. 259-264 [doi]
• Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated CircuitsSrinath R. Naidu. 265-270 [doi]
• An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and AnalysisVineet Wason, Rajeev Murgai, William W. Walker. 271-277 [doi]
• Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance VariationRatnakar Goyal, Sachin Shrivastava, Harindranath Parameswaran, Parveen Khurana. 278-282 [doi]
• An ECO Technique for Removing Crosstalk Violations in Clock NetworksAmit Kumar, Krishnendu Chakrabarty, Chunduri Rama Mohan. 283-288 [doi]
• Optimal Crosstalk Shielding Insertion along On-Chip Interconnect TreesBoyan Semerdjiev, Dimitrios Velenis. 289-294 [doi]
• Bounded Delay Timing Analysis Using Boolean SatisfiabilitySuchismita Roy, P. P. Chakrabarti, Pallab Dasgupta. 295-302 [doi]
• A Novel CMOS Full AdderKeivan Navi, Omid Kavehie, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi. 303-307 [doi]
• Delay-Balanced Smart Repeaters for On-Chip Global SignalingRoshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen. 308-313 [doi]
• Small Fan-in Floating-Gate Circuits with Application to an Improved Adder StructureJon Alfredsson, Snorre Aunet, Bengt Oelmann. 314-317 [doi]
• Design of A Fully Pipelined Single-Precision Multiply-Add-Fused UnitGongqiong Li, Zhaolin Li. 318-323 [doi]
• Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 CompressorsSreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas. 324-329 [doi]
• Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit TechniquesClaas Cornelius, Frank Grassert, Siegmar Koppe, Dirk Timmermann. 330-338 [doi]
• Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCsSandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji. 339-344 [doi]
• Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary CodingKedarnath J. Balakrishnan. 345-350 [doi]
• Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and AlgorithmsV. R. Devanathan, C. P. Ravikumar, V. Kamakoti. 351-356 [doi]
• Zero Cost Test Point Insertion Technique for Structured ASICsRajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell. 357-363 [doi]
• Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC DesignsSubir K. Roy, Rubin A. Parekhji. 364-372 [doi]
• Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable SystemsKenji Asano, Junji Kitamichi, Kenichi Kuroda. 373-378 [doi]
• Towards Generic On-the-Fly Reconfigurable Sensor Electronics for Embedded System- First Measurement Results of Reconfigurable FoldedSenthil Kumar Lakshmanan, Peter Tawdross, Andreas König. 379-384 [doi]
• Energy Driven Application SelfAdaptationJorgen Peddersen, Sri Parameswaran. 385-390 [doi]
• Dynamically Optimizing FPGA Applications by Monitoring Temperature and WorkloadsPhillip H. Jones, Young H. Cho, John W. Lockwood. 391-400 [doi]
• A Novel Approach to Domino Circuit SynthesisDhiren M. Parmar, Monalisa Sarma, Debasis Samanta. 401-406 [doi]
• Controllability-driven Power Virus Generation for Digital CircuitsK. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula. 407-412 [doi]
• Detection and Generation of Self-Timed Pipelines from High Level SpecificationsFu-Chiung Cheng, Shu-Ming Chang, Chi-Huam Shieh. 413-418 [doi]
• A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC ArchitecturesBalasubramanian Sethuraman, Ranga Vemuri. 419-426 [doi]
• Temperature-limited microprocessors: Measurements and design implicationsHendrik F. Hamann, Alan J. Weger, James A. Lacey, Zhigang Hu, Pradip Bose, Erwin Cohen, Jamil A. Wakil. 427-432 [doi]
• On-Chip Voltage Down Converter Based on Moderate Inversion for Low- Power VLSI ChipsQianneng Zhou, Fengchang Lai, Yongsheng Wang. 433-438 [doi]
• Statistical Leakage and Timing Optimization for Submicron Process VariationYuanlin Lu, Vishwani D. Agrawal. 439-444 [doi]
• Low Power Sensor Node for a Wireless Sensor NetworkAkepati Sravan, Sujan Kundu, Ajit Pal. 445-450 [doi]
• Power-Efficient Asynchronous DesignYijun Liu, Zhenkun Li, Pinghua Chen, Guangcong Liu. 451-458 [doi]
• Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCsSudarshan Bahukudumbi, Krishnendu Chakrabarty. 459-464 [doi]
• Model Based Test Generation for Microprocessor Architecture ValidationSreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja. 465-472 [doi]
• Spectral RTL Test Generation for MicroprocessorsNitin Yogi, Vishwani D. Agrawal. 473-478 [doi]
• Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m)Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan. 479-484 [doi]
• Test Pattern Generation Using Modulation by Haar Wavelets and Correlation for Sequential BISTSuresh Kumar Devanathan, Michael L. Bushnell. 485-491 [doi]
• A Reduced Complexity Algorithm for Minimizing N-Detect TestsKalyana R. Kantipudi, Vishwani D. Agrawal. 492-497 [doi]
• Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault DiagnosisIrith Pomeranz, Sudhakar M. Reddy. 498-503 [doi]
• Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuitsLoganathan Lingappan, Vijay Gangaram, Niraj K. Jha. 504-512 [doi]
• Automatic Power Modeling of Infrastructure IP for System-on-Chip Power AnalysisNikhil Bansal, Kanishka Lahiri, Anand Raghunathan. 513-520 [doi]
• JouleQuest: An Accurate Power Model for the StarCore DSP PlatformAshish Mathur, Sourav Roy, Rajat Bhatia, Arup Chakraborty, Vijay Bhargava, Jatin Bhartia. 521-526 [doi]
• MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-ChipT. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan. 527-533 [doi]
• Modeling RTOS for Reactive Embedded SystemsWei-Tsun Sun, Zoran Salcic. 534-539 [doi]
• On the Impact of Address Space Assignment on Performance in Systems-on-ChipG. Hazari, Madhav P. Desai, H. Kasture. 540-545 [doi]
• Distributing Congestions in NoCs through a Dynamic Routing Algorithm based on Input and Output SelectionsMasoud Daneshtalab, A. Pedram, Mohammad Hossein Neishaburi, M. Riazati, Ali Afzali-Kusha, Simak Mohammadi. 546-550 [doi]
• Application Specific Datapath Extension with Distributed I/O Functional UnitsNagaraju Pothineni, Anshul Kumar, Kolin Paul. 551-558 [doi]
• STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCsAseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir. 559-564 [doi]
• A 3-dimensional FEM Based Resistance ExtractionSubramanian Rajagopalan, Shabbir H. Batterywala. 565-570 [doi]
• Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale ConvergenceAshish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava. 571-576 [doi]
• Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral SynthesisSaraju P. Mohanty, Elias Kougianos. 577-582 [doi]
• An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading EffectAshesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu. 583-588 [doi]
• A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die CorrelationsSarvesh Bhardwaj, Sarma B. K. Vrudhula. 589-594 [doi]
• Power-efficient Instruction Encoding Optimization for Embedded ProcessorsAnupam Chattopadhyay, Diandian Zhang, David Kammler, Ernst Martin Witte. 595-600 [doi]
• Interpreting and Extending an Analytical Battery Model Using an Iterative Computation MethodNenggan Zheng, Zhaohui Wu, Man Lin, Qijia Wang. 601-608 [doi]
• Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAMMasaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi. 609-614 [doi]
• An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter FunctionQikai Chen, Arjun Guha, Kaushik Roy. 615-620 [doi]
• LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read StabilitySayeed A. Badrudduza, Giby Samson, Lawrence T. Clark. 621-626 [doi]
• Optimum Supply Voltages for Minimization of Leakage Currents in SRAM in Stand-by ModeLava P. Kumar, Baquer Mazhari. 627-631 [doi]
• Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIsDuk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min. 632-637 [doi]
• Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation TechniqueK. R. Viveka, Abhilasha Kawle, Bharadwaj Amrutur. 638-646 [doi]
• Defect-Aware Synthesis of Droplet-Based Microfluidic BiochipsTao Xu, Krishnendu Chakrabarty, Fei Su. 647-652 [doi]
• Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOIJyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin. 653-656 [doi]
• Fault Models and Device Yield of a Large Population of Room Temperature Operation Single-Electron TransistorsDaniel Mazor, Michael L. Bushnell, David J. Mulligan, Richard J. Blaikie. 657-664 [doi]
• A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET TechnologyRajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang. 665-672 [doi]
• Hardware Efficient Piecewise Linear Branch PredictorJiajin Tu, Jian Chen, Lizy K. John. 673-678 [doi]
• A Neural Net Branch Predictor to Reduce PowerRajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell. 679-684 [doi]
• Embedded Support Vector Machine : Architectural Enhancements and EvaluationSoumyajit Dey, Monu Kedia, Niket Agarwal, Anupam Basu. 685-690 [doi]
• Interframe Bus Encoding Technique for Low Power Video CompressionAsral Bahari, Tughrul Arslan, Ahmet T. Erdogan. 691-698 [doi]
• Process Variations and Process-Tolerant DesignSwarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy. 699-704 [doi]
• Scalable techniques and tools for reliability analysis of large circuitsDebayan Bhaduri, Sandeep K. Shukla, Paul Graham, Maya Gokhale. 705-710 [doi]
• Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die VariationsMaryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril. 711-716 [doi]
• Impact of NBTI on FPGAsKrishnan Ramakrishnan, S. Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin. 717-722 [doi]
• On NBTI Degradation Process in Digital Logic CircuitsXiangning Yang, Eric F. Weglarz, Kewal K. Saluja. 723-730 [doi]
• Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-BoxesMatteo Giaconia, Marco Macchetti, Francesco Regazzoni, Kai Schramm. 731-737 [doi]
• A Parallel VLSI Architecture for Layered Decoding for Array LDPC CodesKiran K. Gunnam, Gwan S. Choi, Mark B. Yeary. 738-743 [doi]
• Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless SystemsZahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan. 744-749 [doi]
• A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n)M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas. 750-755 [doi]
• A Power and Area Efficient Maximum Likelihood Detector Implementation for High Throughput MIMO SystemsJ. H. Han, Ahmet T. Erdogan, Tughrul Arslan. 756-762 [doi]
• Delay Test Scan Flip-Flop: DFT for High Coverage Delay TestingGefu Xu, Adit D. Singh. 763-768 [doi]
• Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access ScanKim T. Le, Dong Hyun Baik, Kewal K. Saluja. 769-774 [doi]
• Analog Circuit Testing Using Auto Regressive Moving Average ModelsJeffrey Ayres, Michael L. Bushnell. 775-780 [doi]
• Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test GenerationYoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu. 781-786 [doi]
• Modified Stability Checking for On-line Error DetectionSatish Yada, Bharadwaj Amrutur, Rubin A. Parekhji. 787-792 [doi]
• Low Shift and Capture Power Scan TestsSantiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski. 793-798 [doi]
• Functional Broadside Tests with Different Levels of ReachabilityIrith Pomeranz, Sudhakar M. Reddy. 799-804 [doi]
• Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan ArchitectureEdward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov. 805-812 [doi]
• Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet TransformRahul Jain, Preeti Ranjan Panda. 813-818 [doi]
• A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise PerformanceHimanshu Patel, Sanjay Trivedi, R. Neelkanthan, V. R. Gujraty. 819-823 [doi]
• An Enhanced CAM Architecture to Accelerate LZW Compression AlgorithmRupak Samanta, Rabi N. Mahapatra. 824-829 [doi]
• A Scalable Frame-Level Pipelined Architecture for FSBM Motion EstimationWei-Feng He, Meng-Lian Zhao, Chi-Ying Tsui, Zhi-Gang Mao. 830-835 [doi]
• VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR DecompositionChitranjan K. Singh, Sushma Honnavara Prasad, Poras T. Balsara. 836-841 [doi]
• An Efficient Design of Cellular Automata Based Cryptographically Robust One-Way FunctionDebdeep Mukhopadhyay, Pallavi Joshi, Dipanwita Roy Chowdhury. 842-853 [doi]
• SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition SystemV. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar. 848-853 [doi]
• Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis CountermeasureKarthik Baddam, Mark Zwolinski. 854-862 [doi]
• Parallelization of DC Analysis through Multiport DecompositionGaurav Trivedi, Madhav P. Desai, H. Narayanan. 863-868 [doi]
• Application of DC Analyzer to Combinatorial Optimization ProblemsGaurav Trivedi, Sumit Punglia, H. Narayanan. 869-874 [doi]
• Impact of Modern Process Technologies on the Electrical Parameters of InterconnectsDebjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou. 875-880 [doi]
• A Placement Methodology for Robust ClockingGanesh Venkataraman, Jiang Hu. 881-886 [doi]
• Calibration Based Methods for Substrate Modeling and Noise Analysis for Mixed-Signal SoCscSankar P. Debnath, Ganesh P. Kumar 0002, Sukumar Jairam. 887-892 [doi]
• Floorplanning in Modern FPGAsPritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu. 893-898 [doi]
• Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area MinimizationJin-Tai Yan, Bo-Yi Chiang. 899-906 [doi]
• Design and Testing of an Integrated Circuit for Multi-Electrode Neural RecordingReid R. Harrison, Paul T. Watkins, Ryan J. Kier, Daniel J. Black, Robert O. Lovejoy, Richard A. Normann, Florian Solzbacher. 907-912 [doi]
• A PMOS-diode Differential Body-driven Offset compensated 0.5VS. M. Rezaul Hasan. 913-918 [doi]
• Continuous Time Sigma Delta Modulator Employing a Novel Comparator ArchitectureU. K. Vijay, Amrutur Bharadwaj. 919-924 [doi]
• Programmable Digital Frequency MultiplierSanjay Kumar Wadhwa, Deeya Muhury, Krishna Thakur. 925-928 [doi]
• On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topologyPradipta Patra, Amit Patra, Debaprasad Kastha. 935-940 [doi]
• A CMOS Low Voltage Charge PumpShantanu A. Bhalerao, Abhishek V. Chaudhary, Rajendra M. Patrikar. 941-946 [doi]