Table of Contents

• A New Method for Generating Tests for Delay Faults in Non-Scan CircuitsPrathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth. 4-11 [doi]
• A New Reliable Method for Delay-Fault DiagnosisMarie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. 12-16 [doi]
• Functional Test Generation for Sequential CircuitsJames Jacob, Vishwani D. Agrawal. 17-24 [doi]
• Minimizing Total Wire Length By Flipping ModulesKyunrak Chong, Sartaj Sahni. 25-30 [doi]
• An Effective Timing-Driven Placement Algorithm For Macro CellsChing-Ting Wu, Andrew Lim, David H. C. Du. 31-36 [doi]
• The k-layer Topological Via Minimization Problem on a Circular ChannelJ. S. Huang, Yeh-Hao Chin. 37-42 [doi]
• A Switch-Level Test Generation SystemKent L. Einspahr, Sharad C. Seth. 43-48 [doi]
• On Computing Tests for Bridging and Leakage Faults: Complexity Results and Universal Test SetsSreejit Chakravarty. 49-54 [doi]
• On Bridging Faults in ECL CircuitsSankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya. 55-60 [doi]
• Single Phase Dynamic CMOS POS PLAY. B. Dhong, C. P. Tsang. 61-67 [doi]
• Design Migration Across Technology - Making It WorkSoumitra De Sirkar, Raghuram S. Tupuri, C. Sudha Madhuri, G. Rajagopalan, Kalpesh D. Mehta, C. G. Madhukar, Giridhar Bajpe. 68-72 [doi]
• Analysis of Design Methodology with Logic Cell ArraysRita Cucchiara, Giovanni Neri, G. Rustichelli, Tullio Salmon Cinotti. 73-79 [doi]
• Concurrent Two-Dimensional State Minimization and State Assignment of finite State MachinesMarek A. Perkowski, William Zhao, Douglas V. Hall. 80-84 [doi]
• Interconnect Optimization Techniques in Data Path SynthesisChittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose. 85-90 [doi]
• Towards System level modeling and synthesisAhmed Amine Jerraya, Kevin O'Brien, Inhag Park, Bernard Courtois. 91-96 [doi]
• Optimization Techniques for Pipelined SchedulingDonald A. Lobo, Barry M. Pangrle. 97-102 [doi]
• System Level Specification and SynthesisSanjiv Narayan, Frank Vahid, Daniel D. Gajski. 103-108 [doi]
• Solving Physical Design Problems on a Vector MachineC. P. Ravikumar. 109-116 [doi]
• OPSYN - OASYS Based Pseudosynthesis ToolN. S. Nagaraj. 117-123 [doi]
• Mirroring Silicon Behaviour in ASIC models- The Issues InvolvedMohan Kumar, Sharada Satrasala, Richard Goldman. 124-127 [doi]
• Design And Fabrication Of GaAs 2-input Nor GateHarsh, B. K. Sehgal, V. R. Balakrishnan, S. Mohan, A. A. Naik, P. Agarwal, R. Gulati, R. K. Purohit, Ishwar Chandra. 128-132 [doi]
• A Novel Scheme for Designing Error Correcting Codes Using Cellular AutomataDipanwita Roy Chowdhury, Saugata Basu, Idranil Sen Gupta, Parimal Pal Chaudhuri. 133-136 [doi]
• A Behavioral Fault Simulator For IdealAjay Khoche, Sunil D. Sherlekar, G. Venkatesh. 137-143 [doi]
• An Architecture To Test Random Access MemoriesRochit Rajsuman. 144-147 [doi]
• 3-Weight Pseudo-Random Test Generation Based on a Deterministic Test SetIrith Pomeranz, Sudhakar M. Reddy. 148-153 [doi]
• An Efficient Rule Based Fault SimulatorOommen Tharakan, James Jacob, Mandyam-Komar Srinivas. 154-156 [doi]
• A Low-Cost High-Capacity Associative Memory Design Using Cellular AutomataDipanwita Roy Chowdhury, Idranil Sen Gupta, Parimal Pal Chaudhuri. 157-160 [doi]
• Scalable, Pipelined, Cmos VLSI Content Addressable Memory Chips - Architecture And ImplementationKanad Ghose, Arun Gupta. 161-166 [doi]
• An Array Architecture for Computing KLT Basis VectorsAnindya Sundar Dhar. 167-170 [doi]
• Design and Implementation of High Speed RNS Input-Output ConvertersKalpesh D. Mehta, V. R. Sudershan. 171-174 [doi]
• Estimating the Complexity of Synthesized Designs from FSM SpecificationsBiswadip Mitra, Preeti Ranjan Panda, Parimal Pal Chaudhuri. 175-180 [doi]
• A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In IdeasManu Lauria, Shashi Kumar, Anshul Kumar. 181-186 [doi]
• Combined Synthesis of Easily Testable Datapath and Control DesignsBiswadip Mitra, Parimal Pal Chaudhuri. 187-192 [doi]
• Synthesis of Self-Testable Sequential Logic Using Programmable Cellular AutomataSusanta Misra, Biswadip Mitra, S. Sengupta, Parimal Pal Chaudhuri. 193-198 [doi]
• An Efficient State Assignment Technique using Least Commitment and Constraint Propagation TechniquesBiswadip Mitra, Parimal Pal Chaudhuri. 199-202 [doi]
• Low Power Techniques for Portable Real-time DSP ApplicationsAnantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen. 203-208 [doi]
• A CMOS VLSI Chip for Motion DetectionN. Ranganathan, Rajiv Mehrotra, S. Kurji. 209-214 [doi]
• A Two-dimensional Systolic Array Processor for Image ProcessingN. Ranganathan, Minesh Patell, Patrick McCabe. 215-220 [doi]
• ECube: An Efficient Architecture for Analyzing Time-Varying SpectraMohan Vishwanath, Robert Michael Owens, Mary Jane Irwin. 221-226 [doi]
• A Global Test Point Placement Algorithm of Combinational CircuitsDong Xiang, Daozheng Wei, Shisong Chen. 227-232 [doi]
• Computational Complexity of Test-Point Insertions and DecompositionsNageswara S. V. Rao, Shunichi Toida. 233-238 [doi]
• A New Variable Testability Measure: a Concept for Data-Flow Testability EvaluationM. Jamoussi, B. Kaminaka, D. Mukhedkar. 239-244 [doi]
• An Efficient Method for Computation of SignaturesChin-Foo See, Kewal K. Saluja. 245-250 [doi]
• A Force Directed Hill-Climbing Placement AlgorithmRajib Mall, Lalit M. Patnaik. 251-254 [doi]
• An Algorithm for M Shortest Routes for a NetSubba Rao V. Kalari, M. M. Hasan. 255-258 [doi]
• An Efficient Graph-Theoretic Algorithm for Three-Layer Channel RoutingRajat K. Pal, Ajit Pal. 259-262 [doi]
• N2S: An Automatic Netlist to Schematic generatorB. Naveen, A. Savargaonkar, K. S. Raghunathan. 263-267 [doi]
• Constrained Via Minimisation In Greedy Channel RoutingK. R. Rao, K. S. Raghunathan. 268-272 [doi]
• Minimum Partition for the Space Region of VLSI LayoutPei-Yung Hsiao, Chiao-Yi Lin, Chia-Chun Tsai. 273-276 [doi]
• CPM Pole-Zero Computation Using The Generalized Eigenproblem ApproachRam Singh Rana, A. B. Bhattacharyya. 277-280 [doi]
• A New Accurate and Efficient Timing SimulatorShen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska. 281-286 [doi]
• Stepsize Control in Piecewise Approximate Circuit SimulationChandu Visweswariah. 287-292 [doi]
• Design of an Efficient ASIC for the Control of Microwave OvensChandra Shekhar, A. S. Mandal. 293-296 [doi]
• WCS - A CAD Solution for Worst Case Performance Analysis of Integrated CircuitsS. Nagaraj, N. Padmini, N. S. Nagaraj, R. Ramesh, V. Sachidanand. 297-302 [doi]
• Use of CMOS Technology in Wave PipeliningFabian Klass, J. M. Mulder. 303-308 [doi]
• Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASICVason P. Srini. 309-314 [doi]
• A Designer's Perspective on VLSI Tools and MethodologyJaisimha Bannur. 315-319 [doi]
• A System for Behavior Extraction from FPGA Implementations of Synchronous DesignsMahesh Mehendale. 320-321 [doi]
• Data Path Synthesis With Global Time ConstraintPrashant P. Nedungadi, M. Balakrishnan, Anshul Kumar. 322-323 [doi]
• From Process-Oriented Functional Specifications to Efficient Asynchronous CircuitsVenkatesh Akella, Ganesh Gopalakrishnan. 324-325 [doi]
• Logic Design and Synthesis with IEEE Logic Symbols in the DEMET SystemJukka Lahti, Jorma Kivelä. 326-327 [doi]
• An ASIC for High Performance Stepper Motor ControlK. V. S. H. Rao, A. Kansal, Chandra Shekhar, M. Srinivas, V. N. S. N. Rao. 328-329 [doi]
• EPLDs - a Milestone in the World of Logic DesignH. L. Uma. 330-331 [doi]
• Optimization Of Cut-off Frequency Of High Speed Bipolar Transistors Fabricated In The N-well Of A C-mos Process At Low TemperatureChinmay K. Maiti. 332-333 [doi]
• Using Dedicated Functional Simulator for ASIC Design in Indian ContextK. V. S. H. Rao, Raj Singh, Chandra Shekhar. 334-335 [doi]
• A Simple Model for Lindhard Continuum Potential useful for Channeling SimulationR. Ghosh, S. DasGupta. 336-338 [doi]
• Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance AnalysisAbhijit Dharchoudhury, S. M. Kang. 339-340 [doi]
• A Verification Guide for the Perplexed Designer: Matching Verification Techniques and Design TasksP. A. Subrahmanyam. 341-342 [doi]
• The "G-F" 2-Valued Formula Generating Complete Set of Tests to Multiple FaultsYunhuan Sheng, Shaoqing Li. 343-349 [doi]
• Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test VectorsLew Fock Chong Lew Yan Voon, Christian Dufaza, Christian Landrault. 350-351 [doi]
• A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAsMichel Renovell, M. Ildevert, Yves Bertrand. 352-353 [doi]
• An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-TestAnupam Basu, Thomas Charles Wilson, Dilip K. Banerji, Jayanti C. Majithia. 354-355 [doi]
• An Efficient Method For Characterization Of ASIC CompilersS. S. Janaki, C. Sudha Madhuri, T. S. Raghuram, Soumitra De Sirkar. 356-357 [doi]
• Quad Asynchronous Communication Element (ACE) with FIFOS. Uma Mahesh, Marty Long, Laura Simmons. 358-361 [doi]
• Benchmarking Array ComparatorsSamiha Mourad. 362-363 [doi]
• Systolic Arithmetic ArchitecturesKhaled M. Elleithy. 364-365 [doi]
• Design Considerations for a Flat Panel ControllerMahesh Siddappa. 366-367 [doi]
• A New algorithm for combined PLA foldingChunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose. 368-369 [doi]
• Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction SchemePei-Yung Hsiao, Lih-Der Jang. 370-371 [doi]
• DEFLAN- A delay estimator for floorplannerR. Shanker. 372-373 [doi]
• Structured Construction of VLSI Circuits Using Adjacency ListsM. V. V. Satyanarayana. 374-375 [doi]