Table of Contents

• Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and ControlJacob A. Abraham, Abhijit Chatterjee. 1-2 [doi]
• Approximate ComputingSwagath Venkataramani, Kaushik Roy, Anand Raghunathan. 3-4 [doi]
• Self-Awareness in Cyber-Physical SystemsNikil Dutt, Nima Taherinejad. 5-6 [doi]
• SHAKTI Processors: An Open-Source Hardware InitiativeNeel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti. 7-8 [doi]
• Post-Silicon Validation and DiagnosisKanad Basu, Subhadip Kundu. 9-10 [doi]
• Digital Testing - Basics to Advanced Research IssuesKewal K. Saluja. 11 [doi]
• Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of MulticoresSandip Kundu, Omer Khan. 12-13 [doi]
• Digital Testing of ICs for Automotive ApplicationsNilanjan Mukherjee, Janusz Rajski. 14-16 [doi]
• Demystifying Time Varying Circuits and SystemsShanthi Pavan, Nagendra Krishnapura. 17-18 [doi]
• Trustworthy Cyber Physical SystemsAnuradha Annaswamy, Samarjit Chakraborty, Dip Goswami, S. Ramesh, Marilyn Wolf. 19-20 [doi]
• Adaptive Test Methods for High IC Quality and ReliabilityAdit D. Singh. 21-22 [doi]
• Embedded SecurityIngrid Verbauwhede, Debdeep Mukhopadhyay, Sujoy Sinha Roy. 23 [doi]
• RF System Design of an RFIC Receiver for IoTSusanta Sengupta. 24 [doi]
• SOC Design for Wireless CommunicationsZoran Stamenkovic. 25 [doi]
• An Introduction to VHDL 2008Kausik Datta, Goutam Kumar Bhaumik, Rohit Goel. 26-27 [doi]
• Emulation - Smart Way of Power Estimation and Power Aware VerficationGaurav Saharawat, Praveen Shukla, Saurabh Jain, Subash Nayak. 28-29 [doi]
• Cyber Security of Cyber Physical Systems: Cyber Threats and Defense of Critical InfrastructuresSandeep K. Shukla. 30-31 [doi]
• Neuromorphic Computing Enabled by Spin-Transfer Torque DevicesAbhronil Sengupta, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy. 32-37 [doi]
• Database Search and ATPG - Interdisciplinary Domains and AlgorithmsMuralidharan Venkatasubramanian, Vishwani D. Agrawal. 38-43 [doi]
• Hardware/Software Co-Visualization on the Electronic System Level Using SystemCRolf Drechsler, Jannis Stoppe. 44-49 [doi]
• New Directions in Hardware SecurityMark Tehranipoor. 50-52 [doi]
• The Future of NoCs: New Technologies and ArchitecturesPartha Pratim Pande, Sudeep Pasricha, Hiroki Matsutani. 53-55 [doi]
• Technologies for Safe and Intelligent Transportation SystemsSamarjit Chakraborty, S. Ramesh. 56-58 [doi]
• Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life SciencesTsung-Yi Ho, Shigeru Yamashita, Ansuman Banerjee, Sudip Roy 0001. 59-62 [doi]
• Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence SupportTanya Shreedhar, Sujay Deb. 63-68 [doi]
• A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing LogicSonal Yadav, Vijay Laxmi, Manoj Singh Gaur. 69-74 [doi]
• A Statistical Model for Hybrid Wireless Network on ChipPriyanka Mitra. 75-80 [doi]
• Energy Efficient and Congestion-Aware Router Design for Future NoCsWazir Singh, Sujay Deb. 81-85 [doi]
• SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-ChipSai Vineel Reddy Chittamuru, Sudeep Pasricha. 86-91 [doi]
• Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level CachesShirshendu Das, Hemangee K. Kapoor. 92-97 [doi]
• Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder TransformationFarhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan. 98-103 [doi]
• Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube ArchitecturesIshan G. Thakkar, Sudeep Pasricha. 104-109 [doi]
• Logic Synthesis in Reversible PLANazma Tara, Hafiz Md. Hasan Babu, Nawshi Matin. 110-115 [doi]
• Early Scenario Pruning for Efficient Design Space Exploration in Physical SynthesisMohd Anwar, Sourav Saha, Matthew M. Ziegler, Lakshmi Reddy. 116-121 [doi]
• A Modified SRAM Based Low Power Memory DesignApoorva Pathak, Divyesh Sachan, Harish Peta, Manish Goswami. 122-127 [doi]
• Stochastic Number Generation with Few InputsRitsuko Muguruma, Shigeru Yamashita. 128-133 [doi]
• Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient ApplicationsSunil Dutt, Harsh Patel, Sukumar Nandi, Gaurav Trivedi. 134-139 [doi]
• An Efficient VLSI Architecture for Discrete Hadamard TransformM. Mohamed Asan Basiri, S. K. Noor Mahammad. 140-145 [doi]
• A Gyrator Based Output Resistance Enhancement Scheme for a Differential AmplifierM. V. Prajwal, B. S. Srinivas, S. Shodhan, M. K. Jayaram Reddy, Tonse Laxminidhi. 146-150 [doi]
• A Stacked VCO Architecture for Generating Multi-level Synchronous Control SignalsSamiran Dam, Pradip Mandal. 151-155 [doi]
• A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology Mounted in BGA PackageAnkur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao. 156-161 [doi]
• Power Optimization of LNA for LTE ReceiverVinaya M. M., Roy Paily, Anil Mahanta. 162-167 [doi]
• A Wide-Band Receiver Front-End with Programmable Frequency Selective Input MatchingManas Kumar Lenka, Akash Agrawal, Vishal Khatri, Gaurab Banerjee. 168-173 [doi]
• A 1-tap 10.3125Gb/s Programmable Voltage Mode Line Driver in 28nm CMOS TechnologyR. G. Raghavendra, Balbeer Singh Rathor. 174-178 [doi]
• -1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOIAmit Chhabra, Vikas Rana. 179-184 [doi]
• A New Sense Amplifier Topology with Improved Performance for High Speed SRAM ApplicationsAnil Kumar Gundu, Mohammad S. Hashmi, Anuj Grover. 185-190 [doi]
• A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance LossAshish Kumar, G. S. Visweswaran, Vinay Kumar, Kaushik Saha. 191-195 [doi]
• A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved ArchitectureMahendra Sakare. 196-201 [doi]
• Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM CellA. Venkatareddy, R. Sithara, Kumar Y. B. Nithin, M. H. Vasantha. 202-206 [doi]
• A 1.5mA, 2.4GHz ZigBee/BLE QLMVF Receiver Frond End with Split TCAs in 180nm CMOSSesha Sairam Regulagadda, Purushothama Chary, Rizwan Shaik Peerla, Mohd Abdul Naseeb, Amit Acharyya, P. Rajalaksmi, Ashudeb Dutta. 207-212 [doi]
• Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical ReceiverSaurabh R. Anmadwar, Nandakumar Nambath, Shalabh Gupta. 213-218 [doi]
• An 800µW Peak Power Consumption, 24GHz (K-Band), Super-Regenerative Receiver with 200p J/bit Energy Efficiency, for IoTBadreyya Al Shehhi, Mihai Sanduleanu. 219-223 [doi]
• An Efficient on Chip Power Management Architecture for Solar Energy Harvesting SystemsSaroj Mondal, Roy P. Paily. 224-229 [doi]
• A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data AcquisitionKamlesh Singh, Shanthi Pavan. 230-235 [doi]
• A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOSJayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak. 236-239 [doi]
• System Efficiency Improvement Technique for Automotive Power Management IC Using Maximum Load Current Selector CircuitKrishna Kanth Gowri Avalur, Syed Azeemuddin. 240-245 [doi]
• A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled Sigma-Delta ModulatorJos A. V. Prakash, Babita R. Jose, Jimson Mathew. 246-251 [doi]
• Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated CircuitsLokesh Garg, Vineet Sahula. 252-257 [doi]
• Applying River Formation Dynamics to Analyze VLSI Power Grid NetworksSatyabrata Dash, Krishna Lal Baishnab, Gaurav Trivedi. 258-263 [doi]
• Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge DevicesHrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan. 264-269 [doi]
• A Methodology for Thermal Characterization Abstraction of Integrated Opto-Electronic LayoutsLawrence M. Schlitt, Priyank Kalla, Steve Blair. 270-275 [doi]
• An Energy Efficient Dynamically Reconfigurable QR Decomposition for Wireless MIMO CommunicationAshish Kumar Pradhan, Soumitra Kumar Nandy. 276-281 [doi]
• A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level ApproachVishnuram Abhinav, Dheeraj Kumar Sinha, Amitabh Chatterjee, Forrest Brewer. 282-287 [doi]
• FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on DelayArchana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu. 288-293 [doi]
• Analytical Modeling of Dual Material Gate All around Stack Architecture of Tunnel FETN. B. Balamurugan, G. LakshmiPriya, S. Manikandan, G. Srimathi. 294-299 [doi]
• Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up MechanismSourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha. 300-305 [doi]
• Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient ComputingSadulla Shaik, Kalva Sri Rama Krishna, Ramesh Vaddi. 306-311 [doi]
• A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FETDheeraj Kumar Sinha, Amitabh Chatterjee, Vishnuram Abhinav, Gaurav Trivedi, Victor Koldyaev. 312-317 [doi]
• Write Assist Scheme to Enhance SRAM Cell Reliability Using Voltage Sensing TechniqueRajat Gupta, Vijit Gadi, H. Anirudh Upendar. 318-322 [doi]
• Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS TransistorsApoorva Ojha, Narendra Parihar, Nihar R. Mohapatra. 323-327 [doi]
• Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator ConvergenceChandan Yadav, Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Yogesh Singh Chauhan. 328-333 [doi]
• Al/HfO2/Si Gate Stack with Improved Physical and Electrical ParametersRakesh Prasher, Devi Dass, Rakesh Vaid. 334-337 [doi]
• A Quasi-Static Model for the Coupling Impedance between Coplanar Rectangular Contacts on a Bulk SubstrateA. Anvar, Shreepad Karmalkar, R. Gokul, C. Akhil. 338-342 [doi]
• A Generic Implementation of Barriers Using Optical InterconnectsSandeep Chandran, Eldhose Peter, Preeti Ranjan Panda, Smruti R. Sarangi. 349-354 [doi]
• ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic BiochipsAbhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa, Shigeru Yamashita. 355-360 [doi]
• Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar GasesSarvesh Agarwal, S. K. Manhas, Sudeb Dasgupta, Neeraj Jain. 361-366 [doi]
• Nanostructured Silicon Oxide Immunosensor Integrated with Noise Spectroscopy Electronics for POC DiagnosticsN. Das, N. Samanta, C. Roy Chaudhuri. 367-372 [doi]
• E3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-volatile MemoriesShivam Swami, Kartik Mohanram. 373-378 [doi]
• Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary InputsArindam Banerjee, Debesh Kumar Das. 385-390 [doi]
• VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural NetworksGopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan. 391-396 [doi]
• Software Coherence Management on Non-coherent Cache Multi-coresJian Cai, Aviral Shrivastava. 397-402 [doi]
• Partitioned Fair Round Robin: A Fast and Accurate QoS Aware Scheduler for Embedded SystemsArnab Sarkar, Arijit Mondal. 403-408 [doi]
• Relaxation Based Circuit Simulation Acceleration over CPU-FPGAVinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar. 409-414 [doi]
• Efficient Realization of Table Look-Up Based Double Precision Floating Point ArithmeticFarhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan. 415-420 [doi]
• Design and Implementation of Blind Assistance System Using Real Time Stereo Vision AlgorithmsVaddi Chandra Sekhar, Satyajit Bora, Monalisa Dash, Manchi Pavan Kumar, S. Josephine, Roy Paily. 421-426 [doi]
• Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics ExperimentJubin Mitra, Shuaib Ahmad Khan, Rourab Paul, Sanjoy Mukherjee, Amlan Chakrabarti, Tapan Kumar Nayak. 427-432 [doi]
• Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAsAyan Palchaudhuri, Anindya Sundar Dhar. 433-438 [doi]
• A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGASaugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa. 439-444 [doi]
• An Improved Design of a Reversible Fault Tolerant LUT-based FPGAMubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu. 445-450 [doi]
• A Modified Hill Climbing Based Watershed Algorithm and Its Real Time FPGA ImplementationPradipta Roy, Prabir K. Biswas, B. K. Das. 451-456 [doi]
• An Efficient Hardware Implementation of Canny Edge Detection AlgorithmD. Sangeetha, P. Deepa. 457-462 [doi]
• TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering AlgorithmSabyasachi Deyati, Barry John Muldrey, Abhijit Chatterjee. 463-468 [doi]
• Fault Modeling and Simulation of MEDA Based Digital Microfluidics BiochipsVineeta Shukla, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Nor Hisham Hamid, Madiha A. Sheikh. 469-474 [doi]
• Thermal-Safe Schedule Generation for System-on-Chip TestingRajit Karmakar, Santanu Chattopadhyay. 475-480 [doi]
• Fault Tolerance through Invariant Checking for Iterative SolversFelix Loh, Kewal K. Saluja, Parameswaran Ramanathan. 481-486 [doi]
• Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge DefectsG. Cardoso Medeiros, Letícia Maria Bolzani Pöhls, Fabian Vargas. 487-492 [doi]
• Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage DomainsDebjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma. 493-498 [doi]
• ChADD: An ADD Based Chisel Compiler with Reduced Syntactic VarianceVikas Chauhan, Neel Gala, V. Kamakoti. 499-504 [doi]
• An Efficient Method for Clock Skew Scheduling to Reduce Peak CurrentArunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu. 505-510 [doi]
• Path Based Timing Validation for Timed Asynchronous DesignWilliam Lee, Tannu Sharma, Kenneth S. Stevens. 511-516 [doi]
• Symptomatic Bug Localization for Functional Debug of Hardware DesignsDebjit Pal, Shobha Vasudevan. 517-522 [doi]
• A Tiny Coprocessor for Elliptic Curve Cryptography over the 256-bit NIST Prime FieldJeroen Bosmans, Sujoy Sinha Roy, Kimmo Järvinen, Ingrid Verbauwhede. 523-528 [doi]
• A Practical Template Attack on MICKEY-128 2.0 Using PSO Generated IVs and LS-SVMAbhishek Chakraborty, Debdeep Mukhopadhyay. 529-534 [doi]
• Memristor Based Arbiter PUF: Cryptanalysis Threat and Its MitigationUrbi Chatterjee, Rajat Subhra Chakraborty, Jimson Mathew, Dhiraj K. Pradhan. 535-540 [doi]
• Security Metrics for Power Based SCA Resistant Hardware ImplementationJungmin Park, Akhilesh Tyagi. 541-546 [doi]
• Formal Security Verification of Third Party Intellectual Property Cores for Information LeakageJeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri. 547-552 [doi]
• A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked LoopPallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta. 553-554 [doi]
• A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFEPragya Maheshwari, Suhas Kaushik, Mahendra Sakare, Shalabh Gupta. 555-556 [doi]
• A 100-nW Sensitive RF-to-DC CMOS Rectifier for Energy Harvesting ApplicationsShouri Chatterjee, Mohd Tarique. 557-558 [doi]
• A Digitally Assisted Radiation Hardened Current Steering DACAbishek Thekkeyil Kunnath, Bibhudatta Sahoo. 559-560 [doi]
• Improving Reliability and Energy Requirements of Memory in Body Sensor NetworksHarsh N. Patel, Farah B. Yahya, Benton H. Calhoun. 561-562 [doi]
• Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of ProcessorsSudarshan Srinivasan, Nithesh kurella, Israel Koren, Sandip Kundu. 563-564 [doi]
• Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPUSriram Sundaram, Sriram Samabmurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger. 565-566 [doi]
• A Hybrid Energy Efficient Digital ComparatorSyed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas. 567-568 [doi]
• Modeling of Linear Variable Differential TransformerDebashish Sahu, Siddhartha Hazra, Prajit Nandi. 569-570 [doi]
• Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V TransistorChandan Yadav, Amit Agarwal, Yogesh Singh Chauhan. 571-572 [doi]
• Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate LibraryLaxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman. 573-574 [doi]
• Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition DefectBibhash Sen, Rajdeep Kumar Nath, Rijoy Mukherjee, Yashraj Sahu, Biplab K. Sikdar. 575-576 [doi]
• FPGA-based Design of a Hearing Aid with Frequency Response Selection through Audio InputShankarayya G. Kambalimath, Prem C. Pandey, Pandurangarao N. Kulkarni, Shivaling S. Mahant-Shetti, Sangamesh G. Hiremath. 579-580 [doi]
• Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 StandardManchi Pavan Kumar, Roy Paily, Anup Kumar Gogoi. 581-582 [doi]
• Design and Simulation of Microfluidic Components towards Development of a Controlled Drug Delivery PlatformRicha Mishra, Tarun Kanti Bhattacharyya, Tapas Kumar Maity. 583-584 [doi]
• Using Tweaks to Design Fault Resistant CiphersSikhar Patranabis, Debapriya Basu Roy, Debdeep Mukhopadhyay. 585-586 [doi]
• BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS AttacksVinayaka Jyothi, Xueyang Wang, Sateesh Addepalli, Ramesh Karri. 587-588 [doi]
• Test Generation for Hybrid Systems Using Clustering and Learning TechniquesSudhi Proch, Prabhat Mishra. 589-590 [doi]
• Mixed Mode Simulation and Verification of SSCG PLL through Real Value ModelingPallavi Das, Jitendra Yadav, Sujay Deb. 591-592 [doi]
• Test Time Minimisation in Scan Compression Designs Using Dynamic Channel AllocationJais Abraham, Shankar Umapathi, Sumitha Krishnamurthi. 593-594 [doi]
• A Novel EPE Aware Hybrid Global Route Planner after FloorplanningBapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal. 595-596 [doi]
• MSimDRAM: Formal Model Driven Development of a DRAM SimulatorDebiprasanna Sahoo, Manoranjan Satpathy. 597-598 [doi]
• Design and Implementation of Area-Efficient and Low-Power Configurable Booth-MultiplierRahul Shrestha, Utkarsh Rastogiy. 599-600 [doi]
• RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC KernelsSaptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan. 601-602 [doi]
• Reconfiguration Performance Recovery on Optically Reconfigurable Gate ArraysTomoya Akabe, Minoru Watanabe. 603-604 [doi]