Table of Contents

• Two-Step Residue Transfer Technique for High-Speed Pipeline A/DsSudipta Sarkar, Yongda Cai, Anubhav Adak. 3-8 [doi]
• A Low Power Multi-channel Input Delta-Sigma ADC without ResetAshwin Kumar Siva Kumar, Debasish Behera, Nagendra Krishnapura. 9-14 [doi]
• A Clock Retiming Circuit for Repeaterless Low Swing On-Chip InterconnectsNaveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 15-20 [doi]
• On-Chip Non-intrusive Temperature Detection and Compensation of a Fully Integrated CMOS RF Power AmplifierJaved S. Gaggatur, Immanuel Raja, Gaurab Banerjee. 21-26 [doi]
• Towards a Better Lifetime for Non-volatile Caches in Chip MultiprocessorsSukarn Agarwal, Hemangee K. Kapoor. 29-34 [doi]
• An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip MultiprocessorsDebiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam. 35-40 [doi]
• DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write LatencyIshan G. Thakkar, Sudeep Pasricha. 41-46 [doi]
• Virtual Two-Port Memory Architecture for Asymmetric Memory TechnologiesJiayin Li, Kartik Mohanram. 47-52 [doi]
• An FPGA Based High throughput Discrete Kalman Filter Architecture for Real-Time Image DenoisingBibin Johnson, Nimin Thomas, J. Sheeba Rani. 55-60 [doi]
• Efficient Scale Invariant Human Detection Using Histogram of Oriented Gradients for IoT ServicesD. Sangeetha, P. Deepa. 61-66 [doi]
• DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable ArchitecturesManideepa Mukherjee, Alexander Fell, Apala Guha. 67-72 [doi]
• Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in MultiprocessorsShounak Chakraborty, Hemangee K. Kapoor. 75-80 [doi]
• A 50nW Voltage Monitor Scheme for Minimum Energy Sensor SystemsAnand Savanth, Alex S. Weddell, James Myers, David Flynn, Bashir M. Al-Hashimi. 81-86 [doi]
• Energy-Efficient Transceiver for Wireless NoCHemanta Kumar Mondal, Shashwat Kaushik, Sri Harsha Gade, Sujay Deb. 87-92 [doi]
• A Single Inductor, Single Input Dual Output (SIDO) Piezoelectric Energy Harvesting SystemSumit Naikwad, Murali K. Rajendran, Priya Sunil, Ashudeb Dutta. 95-100 [doi]
• Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-designSaransh Sharma, Avilash Mukherjee, Abhishek Dongre, Mrigank Sharad. 101-106 [doi]
• Markov Chain Model Using Lévy Flight for VLSI Power Grid AnalysisSukanta Dey, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi. 107-112 [doi]
• Design of Coherence Verification Unit for Heterogeneous CMPs Integrating Update and Invalidate ProtocolsBidesh Chakraborty, Mamata Dalui, Biplab K. Sikdar. 115-120 [doi]
• High Performance Integer DCT Architectures for HEVCM. Mohamed Asan Basiri, Sk. Noor Mahammad. 121-126 [doi]
• Low Complexity and Critical Path Based VLSI Architecture for LMS Adaptive Filter Using Distributed ArithmeticMphd Tasleem Khan, Shaik Rafi Ahamed, Forrest Brewer. 127-132 [doi]
• Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim ModelPascal Raiola, Dominik Erb, Sudhakar M. Reddy, Bernd Becker 0001. 135-140 [doi]
• Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value AlgebraPrasenjit Biswas, D. M. H. Walker. 141-146 [doi]
• A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon ValidationBinod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita. 147-152 [doi]
• A Study of Power Supply Variation as a Source of Random NoiseFatemeh Tehranipoor, Nima Karimian, Wei Yan, John A. Chandy. 155-160 [doi]
• Compact Implementations of FPGA-based PUFs with Enhanced PerformanceN. Nalla Anandakumar, Mohammad S. Hashmi, Somitra Kumar Sanadhya. 161-166 [doi]
• NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis AttacksDarshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran. 167-172 [doi]
• LNA-LO Co-design Considerations for Low Intermediate Frequency Receivers in 401-406 MHz MedRadio Spectrum for Healthcare ApplicationsAbhishek Srivastava, Nithin Sankar, Devarshi Mrinal Das, Maryam Shojaei Baghini. 175-180 [doi]
• Optimization of 2.4 GHz CMOS Low Noise Amplifier Using Hybrid Particle Swarm Optimization with Lévy FlightDeepak Joshi, Satyabrata Dash, Ayush Malhotra, Pulimi Venkata Sai, Rahul Das, Dikshit Sharma, Gaurav Trivedi. 181-186 [doi]
• A 6V to 42V High Voltage CMOS Bandgap Reference Robust to RF Interference for Automotive ApplicationsSanjeev Nyshadham, A. G. Krishna Kanth. 187-192 [doi]
• Programmable Output Multi-phase Switched Capacitor Step-Up DC-DC Converter with SAR-based RegulationMahesh Zanwar, Subhajit Sen. 193-198 [doi]
• High Gain Capacitance Sensor Interface for the Monitoring of Cell Volume GrowthJaved S. Gaggatur, Gaurab Banerjee. 201-206 [doi]
• DTLB: Deterministic TLB for Tightly Bound Hard Real-Time SystemsKajal Varma, Geeta Patil, Biju K. Raveendran. 207-212 [doi]
• MAVI: An Embedded Device to Assist Mobility of Visually ImpairedRajesh Kedia, K. K. Yoosuf, Pappireddy Dedeepya, Munib Fazal, Chetan Arora, M. Balakrishnan. 213-218 [doi]
• Migration Aware Low Overhead ERfair SchedulerAnshuman Tripathi, Arnab Sarkar, P. P. Chakrabarti. 219-224 [doi]
• Dynamic Power Optimization Based on Formal Property Checking of OperationsShrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz. 227-232 [doi]
• Generating AMS Behavioral Models with Formal Guarantees on Feature AccuracyAntonio Anastasio Bruto da Costa, Pallab Dasgupta. 233-238 [doi]
• Formal Verification of Power Management Logic with Mixed-Signal DomainsSudipa Mandal, Antonio Bruto Da Costa, Aritra Hazra, Pallab Dasgupta, Bhushan Naware, Chunduri Rama Mohan, Sanjib Basu. 239-244 [doi]
• Feature Based Identification of Transmission Line Faults by Synchronous Monitoring of PMUsAntara Ain, Akshay Mambakam, Pallab Dasgupta, Siddhartha Mukhopadhyay. 245-250 [doi]
• A High Performance Switchable Multiband Inductor Structure for LC-VCOsR. R. Manikandan, Venkata Narayana Rao Vanukuru. 253-258 [doi]
• High Accuracy, Multi-output Bandgap Reference Circuit in 16nm FinFetSanjay Kumar Wadhwa, Nidhi Chaudhry. 259-262 [doi]
• A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFETVinay Kumar, Nikhil Puri, Sudhir Kumar, Sumit Srivastav. 269-274 [doi]
• Efficient Binary Basic Linear Algebra Operations on ReRAM Crossbar ArraysDebjyoti Bhattacharjee, Anupam Chattopadhyay. 277-282 [doi]
• Extraction and Analysis of Mobility in Double Gate Junctionless TransistorY. V. Bhuvaneshwari, Abhinav Kranti. 283-288 [doi]
• Improved NCV Gate Realization of Arbitrary Size Toffoli GatesAbhoy Kole, Kamalika Datta. 289-294 [doi]
• Heuristic Based Majority/Minority Logic Synthesis for Emerging TechnologiesVipul Kumar Mishra, Himanshu Thapliyal. 295-300 [doi]
• A 64b/66b Line Encoding for High Speed SerializersSatyajit Mohapatra, Hari Shanker Gupta, Jatindeep Singh, Nihar Ranjan Mohapatra. 303-308 [doi]
• Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET TechnologyMitesh Limachia, Pathik Viramgama, Rajesh Thakker, Nikhil Kothari. 309-314 [doi]
• Within-Die Threshold Voltage Variability Estimation Using Reconfigurable Ring OscillatorPoorvi Jain, Bishnu Prasad Das. 315-320 [doi]
• Clock Skew Measurement Using an All-Digital Sigma-Delta Time to Digital ConverterMahadev Govind Shirwaikar, Naveen Kadayinti, Dinesh Kumar Sharma. 321-326 [doi]
• A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-AmpAnjali Gopinath, Ravi Kumar Adusumalli, Veeresh Babu Vulligaddala, M. B. Srinivas. 329-334 [doi]
• A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAMBhupendra Singh Reniwal, P. Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma. 335-340 [doi]
• A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory AccessVenkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat. 341-346 [doi]
• Frequency Enhancement in Miller Divider with Injection-Locking PortraitMohammed Umar Shaikh, Sivaramakrishna Rudrapati, Nandish Bharat Thaker, Shalabh Gupta. 347-352 [doi]
• A Novel Approach towards Biochemical Synthesis on Cyberphysical Digital Microfluidic BiochipSarit Chakraborty, Susanta Chakraborty. 355-360 [doi]
• ESD Behavior of AlGaN/GaN HEMT on Si: Physical Insights, Design Aspects, Cumulative Degradation and Failure AnalysisBhawani Shankar, Ankit Soni, Manikant Singh, Rohith Soman, K. N. Bhat, Srinivasan Raghavan, Navakanta Bhat, Mayank Shrivastava. 361-365 [doi]
• Electrical Modeling and Characterization of Copper/Carbon Nanotubes in Tapered through Silicon ViasMadhav Rao. 366-371 [doi]
• Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICsDebasri Saha, Susmita Sur-Kolay. 372-377 [doi]
• Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETsAvirup Dasgupta, Chetan Gupta, Anupam Dutta, Yen-Kai Lin, Srikanth Srihari, Ethirajan Tamilmani, Chenming Hu, Yogesh Singh Chauhan. 381-384 [doi]
• DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion RegionsRajat Vishnoi, Pratyush Panday, M. Jagadesh Kumar. 385-390 [doi]
• Physics of Current Filamentation in ggNMOS Revisited: Was Our Understanding Scientifically Complete?Milova Paul, Christian Russ, B. Sampath Kumar, Harald Gossner, Mayank Shrivastava. 391-394 [doi]
• On Testing of Superscalar Processors in Functional Mode for Delay FaultsNihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh. 397-402 [doi]
• Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on HardwareBarry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee. 403-408 [doi]
• Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register FileSparsh Mittal, Haonan Wang, Adwait Jog, Jeffrey S. Vetter. 409-414 [doi]
• Self Aware SoC Security to Counteract Delay Inducing Hardware Trojans at RuntimeKrishnendu Guha, Debasri Saha, Amlan Chakrabarti. 417-422 [doi]
• Hardware Software Codesign for a Hybrid Substitution BoxK. B. Anuroop, Anu James, M. Neema. 423-428 [doi]
• A New Logic Encryption Strategy Ensuring Key InterdependencyRajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta 0001. 429-434 [doi]
• A Systematic Study on the Hysteresis Behaviour and Reliability of MoS2 FETAdil Meersha, B. Sathyajit, Mayank Shrivastava. 437-440 [doi]
• Suppressing Single Transistor Latch Effect in Energy Efficient Steep Switching Junctionless MOSFETsManish Gupta, Abhinav Kranti. 441-446 [doi]
• Hybrid OPC Technique for Fast and Accurate Lithography SimulationPardeep Kumar, S. Srivatsa, P. Mantripragada, S. Upreti, K. V. Shravya. 447-450 [doi]