Table of Contents

• Message from the Steering Committee ChairVishwani D. Agrawal. [doi]
• Message from the Technical Program Co-ChairsDavid Atienza, Subhasish Mitra, Manan Suri. [doi]
• Message from the Tutorial Co-ChairsAmir Aminifar, Shabbir Batterywala. [doi]
• Message from the General Co-ChairsSumit Goswami, Veeresh Shetty. [doi]
• Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and SystemsPriyadarshini Panda, Kaushik Roy 0001. 1-18 [doi]
• A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-RadioAnuj Verma, Rahul Shrestha. 1-6 [doi]
• Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live UpdateAbdelrahman Hosny, Andrew B. Kahng. 1-14 [doi]
• Keynote: Technology directions for a bright semiconductor futureSuk Lee. 1-8 [doi]
• Power Efficient Sense Amplifier For Emerging Non Volatile MemoriesVivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Marco Pasotti. 7-12 [doi]
• Fault Tolerance through Invariant Checking for the Lanczos EigensolverFelix Loh, Kewal K. Saluja, Parameswaran Ramanathan. 13-18 [doi]
• Non-parametric Statistical Density Function Synthesizer and Monte Carlo Sampler in CMOSAhish Shylendra, Sina Haji Alizad, Priyesh Shukla, Amit Ranjan Trivedi. 19-24 [doi]
• A Novel Low Power Ternary Multiplier Design using CNFETsHarita Sirugudi, Sharvani Gadgil, Chetan Vudadha. 25-30 [doi]
• °C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical ApplicationsMounika Kelam, Balaji Yadav Battu, Zia Abbas. 31-36 [doi]
• Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS TechnologyVinay Patil, Anuj Grover, Anuj Parashar. 37-42 [doi]
• User-centric Resource Management for Embedded Multi-core ProcessorsElham Shamsa, Anil Kanduri, Nima Taherinejad, Alma Pröbstl, Samarjit Chakraborty, Amir M. Rahmani, Pasi Liljeberg. 43-48 [doi]
• Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCsMarcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 49-54 [doi]
• Efficient Quantum Circuits for Square-Root and Inverse Square-RootSrijit Dutta, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay. 55-60 [doi]
• Alternative Reduced Hardware MASHI-I-I Digital Delta Sigma ArchitecturePrasad Kulkarni. 61-66 [doi]
• Enhancing the Phase-Noise-Figure-of-Merit of a Resonator using Frequency TransformationsSreeni Poolakkal, Nagarjuna Nallam. 67-71 [doi]
• The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD)Satyajit Mohapatra, Nihar Ranjan Mohapatra. 72-77 [doi]
• A Shared-Memory Parallel Implementation of the RePlAce Global Cell PlacerFrédéric Gessler, Philip Brisk, Mirjana Stojilovic. 78-83 [doi]
• A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic UnitsHassaan Saadat, Tuo Li 0001, Haris Javaid, Sri Parameswaran. 84-89 [doi]
• Area and Energy Efficient Approximate Square Rooters for Error Resilient ApplicationsNeelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma 0001. 90-95 [doi]
• A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound SystemsPurnendu Bhattaru, Nagendra Krishnapura. 96-100 [doi]
• A Low Overhead Methodology for Validating Memory Consistency Models in Chip MultiprocessorsBinod Kumar 0001, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh. 101-106 [doi]
• Analyzing Hardware Security Properties of Processors through Model CheckingBinod Kumar 0001, Akshay Kumar Jaiswal, V. S. Vineesh, Rushikesh Shinde. 107-112 [doi]
• VLSI based Adaptive Power Management Architecture for ECG Monitoring in WBANJitumani Sarma, Rakesh Biswas. 113-118 [doi]
• CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal DesignsSayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian. 119-124 [doi]
• Thermal Load-aware Adaptive Scheduling for Heterogeneous PlatformsSrijeeta Maity, Anirban Ghose, Soumyajit Dey, Swarnendu Biswas. 125-130 [doi]
• FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit SimulationYogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar. 131-136 [doi]
• Cacheline Utilization-Aware Link Traffic Compression for Modular GPUsKishore Punniyamurthy, Shomit Das, Andreas Gerstlauer. 137-142 [doi]
• A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud EnvironmentKrishnendu Guha, Debasri Saha, Amlan Chakrabarti. 143-148 [doi]
• Dissecting Convolutional Neural Networks for Efficient Implementation on Constrained PlatformsVishalini R. Laguduva, Shakil Mahmud, Sathyanarayanan N. Aakur, Robert Karam, Srinivas Katkoori. 149-154 [doi]
• E2GC: Energy-efficient Group Convolution in Deep Neural NetworksNandan Kumar Jha, Rajat Saini, Subhrajit Nag, Sparsh Mittal. 155-160 [doi]
• A Low Noise, Low Power, Wide Range Programmable Output Reference Buffer for Sensor ApplicationsPrudhvi Raj Thota, Kiran Wadagavi, Namani Rakesh, Sumit Bhat, Abirmoya Santra. 161-164 [doi]
• A Novel Methodology of PWM/PFM Mode Transition for Inverting Buck-Boost and Boost Converter for AMOLED Display ApplicationsVenkatesh Kadlimatti, Prudhvi Thota, Sumit Bhat. 165-170 [doi]
• StateLock: State Transition Based Logic Locking for Sequential CircuitsYasaswy Kasarabada, Ranga Vemuri. 171-176 [doi]
• A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural NetworksJoydeep Kumar Devnath, Neelam Surana, Joycee Mekie. 177-182 [doi]
• FPGA based convolution and memory architecture for Convolutional Neural NetworkK. A. Shahan, J. Sheeba Rani. 183-188 [doi]
• On the Effect of Aging on Digital SensorsMd Toufiq Hasan Anik, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi. 189-194 [doi]
• Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number GenerationArjun Singh Chauhan, Vineet Sahula, A. S. Mandal, Abhigyan Dutta. 195-200 [doi]
• Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task SchedulingAshutosh Dhar, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, Deming Chen. 201-206 [doi]
• A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic ArchitectureAneesh Raveendran, Sandra Jean, Mervin J, Vivian Desalphine, David Selvakumar. 207-212 [doi]
• A Design Optimization for Pin-Constrained Paper-based Digital Microfluidic Biochips Integrating Fluid-Control Co-Design IssuesPiyali Datta, Arpan Chakraborty, Rajat Kumar Pal. 213-218 [doi]
• An Accurate, Power and Area Efficient 13.33x Charge Pump with Wide-Range Programmability for Biomedical SensorsAmit Patil, Sumit Bhat, Abirmoya Santra. 219-224 [doi]