Table of Contents

• Identifying sequentially untestable faults using illegal statesDavid E. Long, Mahesh A. Iyer, Miron Abramovici. 4-11 [doi]
• Redundancy Removal and Test Generation for Circuits with Non-Boolean PrimitivesSrimat T. Chakradhar, Steven G. Rothweiler. 12-19 [doi]
• High-level test generation using physically-induced faultsMark C. Hansen, John P. Hayes. 20-28 [doi]
• A portable ATPG tool for parallel and distributed systemsFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva. 29-34 [doi]
• Testing combinational iterative logic arrays for realistic faultsDimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis. 35-41 [doi]
• Verification of transient response of linear analog circuitsAshok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham. 42-47 [doi]
• A solution for the on-line test of analog ladder filtersDiego Vázquez, Adoración Rueda, José L. Huertas. 48-53 [doi]
• Frequency-based BIST for analog circuit testinKhaled Saab, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski. 54-59 [doi]
• A low cost 100 MHz analog test busStephen K. Sunter. 60-65 [doi]
• Self-test in a VCM driver chipLahouari Sebaa, Norm Gardner, Robert Neidorff, Rich Valley. 66-73 [doi]
• On the decline of testing efficiency as fault coverage approaches 100 Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams. 74-83 [doi]
• The use of IDDQ testing in low stuck-at coverage situationsPeter C. Maxwell. 84-88 [doi]
• Cyclic stress tests for full scan circuitsVinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel. 89-94 [doi]
• An approach to dynamic power consumption current testing of CMOS ICsJ. A. Segura, M. Roca, D. Mateo, A. Rubio. 95-100 [doi]
• Iddt testing of continuous-time filtersJ. Arguelles, María José López, J. Blanco, Mar Martínez, Salvador Bracho. 101-107 [doi]
• On shrinking wide compressorsJacob Savir. 108-117 [doi]
• Signature analysis and aliasing for sequential circuitsAlbrecht P. Stroele. 118-124 [doi]
• An apparatus for pseudo-deterministic testingShridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao. 125-131 [doi]
• Arithmetic built-in self test for high-level synthesisNilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer. 132-139 [doi]
• Real-time on-board bus testingJeffrey A. Floyd, Matt Perry. 140-151 [doi]
• Resynthesis for sequential circuits designed with a specified initial stateHiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita. 152-157 [doi]
• A distance reduction approach to design for testabilityFrank F. Hsu, Janak H. Patel. 158-163 [doi]
• An optimized testable architecture for finite state machinesTing-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja. 164-169 [doi]
• Testability metrics for synthesis of self-testable designs and effective test plansMahsa Vahidi, Alex Orailoglu. 170-175 [doi]
• RT level testability-driven partitioningXinli Gu. 176-183 [doi]
• The concept of resistance interval: a new parametric model for realistic resistive bridging faultMichel Renovell, P. Huc, Yves Bertrand. 184-189 [doi]
• High level fault modeling of asynchronous circuitsDing Lu, Carol Q. Tong. 190-195 [doi]
• Checking experiments to test latchesSamy Makar, Edward J. McCluskey. 196-201 [doi]
• Testability of floating gate defects in sequential circuitsVíctor H. Champac, Joan Figueras. 202-207 [doi]
• Switch-level modeling of transistor-level stuck-at faultsPeter Lidén, Peter Dahlgren. 208-215 [doi]
• Simulation of at-speed tests for stuck-at faultsTapan J. Chakraborty, Vishwani D. Agrawal. 216-220 [doi]
• VISION: an efficient parallel pattern fault simulator for synchronous sequential circuitsRajesh Nair, Dong Sam Ha. 221-226 [doi]
• Fault coverage analysis of RAM test algorithmsMarc Riedel, Janusz Rajski. 227-234 [doi]
• Reliability evaluation of combinational logic circuits by symbolic simulationAlessandro Bogliolo, Maurizio Damiani, Piero Olivo, Bruno Riccò. 235-243 [doi]
• Improving the efficiency of error identification via signature analysisCharles E. Stroud, T. Raju Damarla. 244-249 [doi]
• Diagnosis of scan path failuresSamantha Edirisooriya, Geetani Edirisooriya. 250-255 [doi]
• Diagnosis of interconnects and FPICs using a structured walking-1 approachTong Liu, Fabrizio Lombardi, José Salinas. 256-261 [doi]
• Detection and location of faults and defects using digital signal processingClaude Thibeault. 262-269 [doi]
• Asynchronous multiple scan chainSridhar Narayanan, Melvin A. Breuer. 270-276 [doi]
• Partial scan designs without using a separate scan clockKwang-Ting Cheng. 277-282 [doi]
• A partial scan methodology for testing self-timed circuitsAjay Khoche, Erik Brunvand. 283-289 [doi]
• On the design of at-speed testable VLSI circuitsMohamed Soufi, Yvon Savaria, Bozena Kaminska. 290-295 [doi]
• Scan testing of micropipelinesO. A. Petlin, Stephen B. Furber. 296-303 [doi]
• Test pattern generation for I/sub DDQ/: increasing test qualityMarcello Dalpasso, Michele Favalli, Piero Olivo. 304-309 [doi]
• Compact test generation for bridging faults under I/sub DDQ/ testingRemata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara. 310-316 [doi]
• CURRENT: a test generation system for I/sub DDQ/ testingUdo Mahlstedt, Jürgen Alt, Matthias Heinitz. 317-323 [doi]
• Detecting I/sub DDQ/ defective CMOS circuits by depoweringJosep Rius, Joan Figueras. 324-329 [doi]
• Test preparation for high coverage of physical defects in CMOS digital ICsMarcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira. 330-337 [doi]
• Improving topological ATPG with symbolic techniquesFulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Uwe Gläser, Heinrich Theodor Vierhaus. 338-343 [doi]
• A scheduling problem in test generationTomoo Inoue, Hironori Maeda, Hideo Fujiwara. 344-349 [doi]
• Detectable perturbations: a paradigm for technology-specific multi-fault test generationAndrej Zemva, Franc Brglez. 350-357 [doi]
• Compact test sets for industrial circuitsM. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor. 358-366 [doi]
• Reducing test application time in scan design schemesBapiraju Vinnakota, Nicholas J. Stessman. 367-373 [doi]
• Generation of high quality tests for functional sensitizable pathsAngela Krstic, Kwang-Ting Cheng. 374-379 [doi]
• Diagnostic of path and gate delay faults in non-scan sequential circuitsPatrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez. 380-386 [doi]
• On the application of local circuit transformations with special emphasis on path delay fault testabilityHarry Hengster, Rolf Drechsler, Bernd Becker. 387-392 [doi]
• Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming Imtiaz P. Shaik, Michael L. Bushnell. 393-399 [doi]
• Multifault testability of delay-testable circuitsWuudiann Ke, Premachandran R. Menon. 400-409 [doi]
• Transformed pseudo-random patterns for BISTNur A. Touba, Edward J. McCluskey. 410-416 [doi]
• A novel pattern generator for near-perfect fault-coverageMitrajit Chatterjee, Dhiraj K. Pradhan. 417-425 [doi]
• Decompression of test data using variable-length seed LFSRsNadime Zacharia, Janusz Rajski, Jerzy Tyszer. 426-433 [doi]
• Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuitsSamir Lejmi, Bozena Kaminska, Bechir Ayari. 434-439 [doi]
• Synthesis of locally exhaustive test pattern generatorsGünter Kemnitz. 440-447 [doi]
• An approach for system tests design and its applicationSamvel K. Shoukourian, Armen G. Kostanian, Valery A. Margarian, Ayman A. Ashour. 448-453 [doi]
• Synthesis of combinational circuits with special fault-handling capabilitieAlessandro Bogliolo, Maurizio Damiani. 454-459 [doi]
• A tool for automatic generation of self-checking data pathsB. Hamdi, Hakim Bederr, Michael Nicolaidis. 460-466 [doi]
• A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniersSteve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen. 467-471 [doi]
• An experimental evaluation of the differential BICS for I/sub DDQ/ testingWalter W. Weber, Adit D. Singh. 472-485 [doi]
• Structural constraints for circular self-test pathsJoan Carletta, Christos A. Papachristou. 486-491 [doi]