Table of Contents

• Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning SchemeAbhijit Jas, C. V. Krishna, Nur A. Touba. 2-8 [doi]
• Compression Technique for Interactive BIST ApplicationDouglas Kay, Samiha Mourad. 9-14 [doi]
• Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath MultipliersMihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian. 15-21 [doi]
• Diagnosis of Tunneling OpensChien-Mo James Li, Edward J. McCluskey. 22-27 [doi]
• On Diagnosing Path Delay Faults in an At-Speed EnvironmentRamesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar. 28-33 [doi]
• On Improving the Accuracy Of Multiple Defect DiagnosisShi-Yu Huang. 34-41 [doi]
• Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data CompressionAnshuman Chandra, Krishnendu Chakrabarty. 42-47 [doi]
• Design of Parameterizable Error-Propagating Space Compactors for Response ObservationA. Morozov, Michael Gössel, Krishnendu Chakrabarty, Bhargab B. Bhattacharya. 48-53 [doi]
• A Geometric-Primitives-Based Compression Scheme for Testing Systems-on-a-ChipAiman El-Maleh, Esam Khan, Saif al Zahir. 54-61 [doi]
• Testable Sequential Circuit Design: A Partition and Resynthesis ApproachRichard M. Chou, Kewal K. Saluja. 62-67 [doi]
• A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test FrequencyMuhammad Nummer, Manoj Sachdev. 68-74 [doi]
• Breaking Correlation to Improve TestabilityKelly A. Ockunzzi, Christos A. Papachristou. 75-81 [doi]
• Partial Reset for Synchronous Sequential Circuits Using Almost Independent Reset SignalsDong Xiang, Yi Xu. 82-87 [doi]
• Multiple Scan Chain Design for Two-Pattern TestingIlia Polian, Bernd Becker. 88-93 [doi]
• Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed TesterDilip K. Bhavsar. 94-101 [doi]
• A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock SignalsTakahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen. 102-110 [doi]
• Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCsAmir Attarha, Mehrdad Nourani. 111-116 [doi]
• Current Measurement for Dynamic Idd TestXiaoyun Sun, Bapiraju Vinnakota. 117-123 [doi]
• Fault Equivalence Identification Using Redundancy Information and Static and Dynamic ExtractionEnamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana. 124-130 [doi]
• Semi-Formal Test Generation for a Block of Industrial DSPJulia Dushina, Mike Benjamin, Daniel Geist. 131-137 [doi]
• Resistive Opens in a Class of CMOS Latches: Analysis and DFTAntonio Zenteno, Víctor H. Champac. 138-144 [doi]
• A Process and Technology-Tolerant IDDQ Method for IC DiagnosisChintan Patel, Jim Plusquellic. 145-152 [doi]
• Guaranteeing Quality throughout the Product Life Cycle: On-Line Test and Repair to the RescueBill Bottoms, Jim Chung, Bernd Koenemann, Glenn Shirley, Lisa Spainhower. 153-154 [doi]
• ITRS Test Chapter 2001: We ll Tell You What We re Doing, You Tell Us What We Should Be DoingMike Rodgers. 155-157 [doi]
• Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan EnvironmentTek Jau Tan, Chung-Len Lee. 158-162 [doi]
• Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip EnvironmentAshish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal. 163-168 [doi]
• High-level Crosstalk Defect Simulation for System-on-Chip InterconnectsXiaoliang Bai, Sujit Dey. 169-177 [doi]
• Design Diversity for Concurrent Error Detection in Sequential Logic CircutsSubhasish Mitra, Edward J. McCluskey. 178-183 [doi]
• Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed DebuggingEgor S. Sogomonyan, A. A. Morosov, Jan Rzeha, Michael Gössel, Adit D. Singh. 184-189 [doi]
• Design of Redundant Systems Protected Against Common-Mode FailuresSubhasish Mitra, Edward J. McCluskey. 190-197 [doi]
• A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCsJing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng. 198-203 [doi]
• Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip BusesWei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng. 204-209 [doi]
• Electrically Induced Stimuli For MEMS Self-TestBenoît Charlot, Salvador Mir, Fabien Parrain, Bernard Courtois. 210-217 [doi]
• Flash Memory Disturbances: Modeling and TestMohammad Gh. Mohammad, Kewal K. Saluja. 218-224 [doi]
• Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor MemoriesKuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu. 225-230 [doi]
• An Efficient Methodology for Generating Optimal and Uniform March TestsSultan M. Al-Harbi, Sandeep K. Gupta. 231-239 [doi]
• RT-level Fault Simulation Based on Symbolic PropagationOzgur Sinanoglu, Alex Orailoglu. 240-245 [doi]
• Efficient Transparency Extraction and Utilization in Hierarchical TestYiorgos Makris, Vishal Patel, Alex Orailoglu. 246-251 [doi]
• Analysis of Testing Methodologies for Custom Designs in PowerPCTM MicroprocessorMagdy S. Abadir, Juhong Zhu, Li-C. Wang. 252-259 [doi]
• Test Waveform Shaping in Mixed Signal Test Bus by Pre-EqualizationYue-Tsang Chen, Chauchin Su. 260-265 [doi]
• A Low-Cost Adaptive Ramp Generator for Analog BIST ApplicationsFlorence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell. 266-271 [doi]
• Self-Testable Pipelined ADC with Low Hardware OverheadEduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas. 272-278 [doi]
• Soft Errors and Tolerance for Soft ErrorsJim Chung, N. Derhacobian, Jean Gasiot, Michael Nicolaidis, David Towne, R. Velazco. 279-280 [doi]
• Yield Optimization and Its Relation to TestTracy Larrabee, Jon Colbum. 281-282 [doi]
• ATPG for Design Errors-Is It Possible?Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma. 283-285 [doi]
• Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and ExperimentsIvan de Paúl, M. Rosales, B. Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden. 286-291 [doi]
• Enabling Embedded Memory Diagnosis via Test Response CompressionJohn T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare. 292-298 [doi]
• Automatic Generation of Diagnostic March TestsDirk Niggemeyer, Elizabeth M. Rudnick. 299-305 [doi]
• A Modified Clock Scheme for a Low Power BIST Test Pattern GeneratorPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich. 306-311 [doi]
• Test Scheduling for Minimal Energy Consumption under Power ConstraintsTobias Schüle, Albrecht P. Stroele. 312-318 [doi]
• Reducing Power Dissipation during Test Using Scan Chain DisableRanganathan Sankaralingam, Nur A. Touba, Bahram Pouya. 319-325 [doi]
• Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability ModelThomas S. Barnett, Adit D. Singh, Victor P. Nelson. 326-332 [doi]
• High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability EnhancementMohammad Athar Khalil, Chin-Long Wey. 333-338 [doi]
• MINVDD Testing for Weak CMOS ICsChao-Wen Tseng, Ray Chen, Edward J. McCluskey, Phil Nigh. 339-345 [doi]
• SPIRIT: A Highly Robust Combinational Test Generation AlgorithmEmil Gizdarski, Hideo Fujiwara. 346-351 [doi]
• On the Use of Fault Dominance in n-Detection Test GenerationIrith Pomeranz, Sudhakar M. Reddy. 352-357 [doi]
• Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-outYi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer. 358-367 [doi]
• Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-ChipVikram Iyengar, Krishnendu Chakrabarty. 368-374 [doi]
• Average Leakage Current Estimation of CMOS Logic CircuitsJosé Pineda de Gyvez, Eric van de Wetering. 375-379 [doi]
• An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication LinksJiun-Lang Huang, Kwang-Ting Cheng. 380-387 [doi]
• Tools for the Characterization of Bipolar CML TestabilityGinette Monté, Bernard Antaki, Serge Patenaude, Yvon Savaria, Claude Thibeault, Pieter M. Trouborst. 388-395 [doi]
• Testing of Dynamic Logic Circuits Based on Charge SharingKeerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton. 396-403 [doi]
• An Evaluation of Pseudo Random Testing for Detecting Real DefectsChao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson. 404-410 [doi]
• IP and Automation to Support IEEE P1500Dwayne Burek, Garen Darbinyan, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti. 411-412 [doi]
• Reliability Beyond GHzPete O Neill, Ron Richmond, Mike Tripp, Barbara Vasquez, Art Wager, Zeev Weinberg. 413-414 [doi]
• Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them?Henry Chang, Steve Dollens, Gordon Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham. 415-416 [doi]