Table of Contents

• Efficient Array Characterization in the UltraSPARC T2Thomas A. Ziaja, Poh J. Tan. 3-8 [doi]
• Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor ControllerMichail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris. 9-14 [doi]
• Modeling and Testing Comparison Faults of TCAMs with Asymmetric CellsYong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li. 15-20 [doi]
• An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short DefectsNicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker. 21-26 [doi]
• Small Delay Fault Model for Intra-Gate Resistive Open DefectsMasayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo. 27-32 [doi]
• Defect Detection Differences between Launch-Off-Shift and Launch-Off-Capture in Sense-Amplifier-Based Flip-Flop TestingHaluk Konuk. 33-38 [doi]
• Soft-Error Hardening Designs of Nanoscale CMOS LatchesSheng Lin, Yong-Bin Kim, Fabrizio Lombardi. 41-46 [doi]
• Exploiting Unused Spare Columns to Improve Memory ECCRudrajit Datta, Nur A. Touba. 47-52 [doi]
• An Adaptive-Rate Error Correction Scheme for NAND Flash MemoryTe-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu. 53-58 [doi]
• Compact Delay Test Generation with a Realistic Low Cost Fault Coverage MetricZheng Wang, Duncan M. Hank Walker. 59-64 [doi]
• Recursive Path Selection for Delay Fault TestingJaeyong Chung, Jacob A. Abraham. 65-70 [doi]
• A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don t Care Path IdentificationYuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara. 71-76 [doi]
• Automated Selection of Signals to Observe for Efficient Silicon DebugJoon-Sung Yang, Nur A. Touba. 79-84 [doi]
• A New Post-Silicon Debug Approach Based on Suspect WindowJianliang Gao, Yinhe Han, Xiaowei Li. 85-90 [doi]
• Automated Debug of Speed Path Failures Using Functional TestsRichard McLaughlin, Srikanth Venkataraman, Carlston Lim. 91-96 [doi]
• Output Hazard-Free Transition Delay Fault Test GenerationSreekumar Menon, Adit D. Singh, Vishwani Agrawal. 97-102 [doi]
• Efficient Scheduling of Path Delay Tests for Latch-Based CircuitsKun Young Chung, Sandeep K. Gupta. 103-110 [doi]
• Effective and Efficient Test Pattern Generation for Small Delay DefectSandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia. 111-116 [doi]
• Panel: Apprentice - VTS Edition: Season 2Kee Sup Kim. 119 [doi]
• DFT and Test Problems from the TrenchesHaluk Konuk. 120 [doi]
• Multiple-Fault Diagnosis Using Faulty-Region IdentificationMeng-Jai Tasi, Mango C.-T. Chao, Jing-Yang Jou, Meng-Chen Wu. 123-128 [doi]
• Predictive Test Technique for Diagnosis of RF CMOS ReceiversKay Suenaga, Sebastiàn A. Bota, Rodrigo Picos, Eugeni Isern, Miquel Roca, Eugeni García-Moreno. 129-133 [doi]
• Controlling DPPM through Volume DiagnosisXiaochun Yu, Yen-Tzu Lin, Wing Chiu Tam, Osei Poku, Ronald D. Blanton. 134-139 [doi]
• Scalable Compact Test Pattern Generation for Path Delay Faults Based on FunctionsEdward Flanigan, Spyros Tragoudas, Arkan Abdulrahman. 140-145 [doi]
• The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test CostZhen Chen, Dong Xiang, Boxue Yin. 146-151 [doi]
• A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip InterconnectionsSunghoon Chun, YongJoon Kim, Taejin Kim, Sungho Kang. 152-157 [doi]
• False Path Aware Timing Yield Estimation under VariabilityLin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar. 161-166 [doi]
• Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case StudyRitesh P. Turakhia, Mark Ward, Sandeep Kumar Goel, Brady Benware. 167-172 [doi]
• Yield and Cost Analysis of a Reliable NoCSaeed Shamshiri, Kwang-Ting Cheng. 173-178 [doi]
• Restrict Encoding for Mixed-Mode BISTAbdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz. 179-184 [doi]
• A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase OffsetKeith A. Jenkins, Lionel Li. 185-188 [doi]
• Experimental Validation of a BIST Techcnique for CMOS Active Pixel SensorsLivier Lizarraga, Salvador Mir, Gilles Sicard. 189-194 [doi]
• Physically-Aware N-Detect Test RelaxationYen-Tzu Lin, Chukwuemeka U. Ezekwe, Ronald D. Blanton. 197-202 [doi]
• Automatic Selection of Internal Observation Signals for Design VerificationTao Lv, Huawei Li, Xiaowei Li. 203-208 [doi]
• STDF Memory Fail Datalog StandardAjay Khoche, Jay Katz, Sauro Landini, Kochen Liao, Neetu Agrawal, Glenn Plowman, Song-lin Zuo, Liyang Lai, John Rowe, Thomas Zanon. 209-214 [doi]
• Testing for Transistor AgingA. Hakan Baba, Subhasish Mitra. 215-220 [doi]
• Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical PathsJunxia Ma, Jeremy Lee, Mohammad Tehranipoor. 221-226 [doi]
• Understanding Power Supply Droop during At-Speed Scan TestingPankaj Pant, Joshua Zelman. 227-232 [doi]
• Special Session 7C: TTTC 2009 Best Doctoral Thesis ContestYiorgos Makris, Haralampos-G. D. Stratigopoulos. 233 [doi]
• Special Session 8: New Topics: At-Speed Testing in the Face of Process VariationsBernard Courtois, Chandu Visweswariah. 237 [doi]
• Microscale and Nanoscale Thermal Characterization of Integrated Circuit ChipsBernard Courtois, Ali Shakouri. 241 [doi]
• Highly X-Tolerant Selective Compaction of Test ResponsesGrzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer. 245-250 [doi]
• Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone MeasureDong Xiang, Boxue Yin, Kwang-Ting Cheng. 251-256 [doi]
• Maintaining Accuracy of Test Compaction through Adaptive Re-learningSounil Biswas, Ronald D. Blanton. 257-263 [doi]
• RT-Level Deviation-Based Grading of Functional Test SequencesHongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti. 264-269 [doi]
• DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case StudyDavide Appello, Paolo Bernardi, Simone Gerardin, Michelangelo Grosso, Alessandro Paccagnella, Paolo Rech, Matteo Sonza Reorda. 276-281 [doi]
• On-Line Calibration and Power Optimization of RF Systems Using a Built-In DetectorChaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham. 285-290 [doi]
• Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADCHsiu-Ming Chang, Chin-Hsuan Chen, Kuan-Yu Lin, Kwang-Ting Cheng. 291-296 [doi]
• A Time Domain Method to Measure Oscillator Phase NoiseKenneth Blakkan, Mani Soma. 297-302 [doi]
• A Packet Based 2x-Site Test Solution for GSM Transceivers with Limited Tester ResourcesErdem Serkan Erdogan, Sule Ozev. 303-308 [doi]
• Design-for-Testability for Digital Microfluidic BiochipsTao Xu, Krishnendu Chakrabarty. 309-314 [doi]
• Stuck-Open Fault Leakage and Testing in Nanometer TechnologiesJulio César Vázquez, Víctor H. Champac, Chuck Hawkins, Jaume Segura. 315-320 [doi]
• SS-KTC: A High-Testability Low-Overhead Scan Architecture with Multi-level Security IntegrationUnni Chandran, Dan Zhao. 321-326 [doi]
• Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGAGaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin. 327-332 [doi]
• Special Session 11C: Embedded Tutorial: System-on-a-Chip Power Management Implications on Validation and TestingBhanu Kapoor. 333 [doi]
• Panel: Analog Characterization and Test: The Long Road to RealizationArani Sinha, Amitava Majumdar, Vasu Ganti. 337 [doi]
• Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough?Andrew Piziali. 338 [doi]