| 1 | -- | 3 | Melissa C. Smith, Kubilay Atasu. Guest Editorial: Application Specific Processors and Architectures |
| 5 | -- | 29 | Srinivas Boppu, Frank Hannig, Jürgen Teich. Compact Code Generation for Tightly-Coupled Processor Arrays |
| 31 | -- | 59 | Jürgen Teich, Alexandru Tanase, Frank Hannig. Symbolic Mapping of Loop Programs onto Processor Arrays |
| 61 | -- | 76 | Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell. Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform |
| 77 | -- | 93 | Christian Pinto, Luca Benini. A Novel Object-Oriented Software Cache for Scratchpad-Based Multi-Core Clusters |
| 95 | -- | 115 | M. Alexandre Carbon, Yves Lhuillier, Henri-Pierre Charles. Hardware Acceleration of Red-Black Tree Management and Application to Just-In-Time Compilation |
| 117 | -- | 129 | Ce Guo, Wayne Luk. Pipelined HAC Estimation Engines for Multivariate Time Series |
| 131 | -- | 149 | Huan Truong, Da Li, Kittisak Sajjapongse, Gavin Conant, Michela Becchi. Large-Scale Pairwise Alignments on GPU Clusters: Exploring the Implementation Space |
| 151 | -- | 167 | Tobias Schneider, Ingo von Maurich, Tim Güneysu, David Oswald. Cryptographic Algorithms on the GA144 Asynchronous Multi-Core Processor - Implementation and Side-Channel Analysis |
| 169 | -- | 190 | Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer. A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores |
| 191 | -- | 205 | Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa. An Efficient Scalable RNS Architecture for Large Dynamic Ranges |
| 207 | -- | 220 | Mark G. Arnold, Sylvain Collange. Options for Denormal Representation in Logarithmic Arithmetic |