| 207 | -- | 208 | Graham A. Jullien. Guest editor s introduction |
| 209 | -- | 225 | Howard C. Card, Christian R. Schneider, Roland S. Schneider. Learning capacitive weights in analog CMOS neural networks |
| 227 | -- | 240 | Calvin Plett, Miles A. Copeland. Self-tuned continuous-time notch filters |
| 241 | -- | 251 | T. C. Davies, Dhamin Al-Khalili, V. Szwarc. A floating-point systolic array processing element with serial communication and built-in self-test |
| 253 | -- | 265 | V. Szwarc, L. Desormeaux, W. Wong, C. P. S. Yeung, C. H. Chan, Tad A. Kwasniewski. A chip set for pipeline and parallel pipeline FFT architectures |
| 267 | -- | 282 | Sudhir M. Gowda, Bing J. Sheu, Wen-Jay Hsu. Testing of programmable analog neural network chips |
| 283 | -- | 291 | Marc Moonen. Implementing the square-root information Kalman filter on a Jacobi-type systolic array |
| 293 | -- | 303 | Patrick Fitzpatrick. On fault tolerant matrix decomposition |
| 305 | -- | 318 | Subir Bandyopadhyay, Graham A. Jullien, Abhijit Sengupta. A fast VLSI systolic array for large modulus residue addition |