Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL

Simen Gimle Hansen, Dirk Koch, Jim Torresen. Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL. In 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013. pages 1-8, IEEE, 2013. [doi]

Abstract

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