Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin. Using Hard Macros to Reduce FPGA Compilation Time. In International Conference on Field Programmable Logic and Applications, FPL 2010, August 31 2010 - September 2, 2010, Milano, Italy. pages 438-441, IEEE, 2010. [doi]
Abstract is missing.