A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division

David W. Matula, Lee D. McFearin. A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division. In Georges G. E. Gielen, editor, Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006. pages 1134-1138, European Design and Automation Association, Leuven, Belgium, 2006. [doi]

Abstract

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