Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure

Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot. Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. In Gilles Sassatelli, Leandro Soares Indrusiak, Manfred Glesner, Lionel Torres, editors, Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006. pages 117-123, Univ. Montpellier II, 2006.

Abstract

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