Abstract is missing.
- The SawMill Framework for Virtual Memory DiversityMohit Aron, Jochen Liedtke, Kevin Elphinstone, Yoonho Park, Trent Jaeger, Luke Deller. 3-10 [doi]
- Adaptive Interfacing with Reconfigurable ComputersNeil W. Bergmann, Anwar S. Dawood. 11-18 [doi]
- Error Detection for Adaptive Computing Architectures in Spacecraft ApplicationsDavid Brodrick, Anwar S. Dawood, Neil W. Bergmann, Melanie Wark. 19-26 [doi]
- Components + Security = OS ExtensibilityAntony Edwards, Gernot Heiser. 27-34 [doi]
- Exploiting Java Instruction/Thread Level Parallelism with Horizontal MultithreadingKenji Watanabe, Wanming Chu, Yamin Li. 35-44 [doi]
- A Simulator for High Speed Digital CommunicationsErnest A. Fardin, Peter Munro, Jarred Scagliotta, John Morris. 45-54 [doi]
- Stacking them up: a Comparison of Virtual MachinesK. John Gough. 55-61 [doi]
- DSTRIDE: Data-Cache Miss-Address-Based Stride Prefetching Scheme for Multimedia ProcessorsG. Hariprakash, R. Achutharaman, Amos Omondi. 62-70 [doi]
- Two Cache Lines Prediction for a Wide-Issue Micro-architectureShu-Lin Hwang, Feipei Lai. 71-79 [doi]
- Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelinesChris R. Jesshope. 80-88 [doi]
- High-Performance Extendable Instruction Set ComputingHeui Lee, Paul Becket, Bill Appelbe. 89-94 [doi]
- Fault-Tolerant Routing on Complete Josephus CubesPeter K. K. Loh, Heiko Schröder, W. I. Hsu. 95-104 [doi]
- Password-Capabilities: Their Evolution from the Password-Capability System into Walnut and BeyondRonald Pose. 105-113 [doi]
- Retargetable Cache Simulation Using High Level Processor ModelsRajiv A. Ravindran, Rajat Moona. 114-129 [doi]
- The First Real Operating System for Reconfigurable ComputersGrant B. Wigley, David A. Kearney. 130-137 [doi]
- Performance Evaluation of a Partial Retraining Scheme for Defective Multi-Layer Neural NetworksKunihito Yamamori, Toru Abe, Susumu Horiguchi. 138-146 [doi]