Abstract is missing.
- Implementing an OpenFlow switch on the NetFPGA platformJad Naous, David Erickson, G. Adam Covington, Guido Appenzeller, Nick McKeown. 1-9 [doi]
- Design of a scalable network programming frameworkBen Wun, Patrick Crowley, Arun Raghunath. 10-18 [doi]
- A remotely accessible network processor-based router for network experimentationCharlie Wiseman, Jonathan S. Turner, Michela Becchi, Patrick Crowley, John D. DeHart, Mart Haitjema, Shakir James, Fred Kuhns, Jing Lu, Jyoti Parwatikar, Ritun Patney, Michael Wilson, Ken Wong, David Zar. 20-29 [doi]
- Compact architecture for high-throughput regular expression matching on FPGAYi-Hua E. Yang, Weirong Jiang, Viktor K. Prasanna. 30-39 [doi]
- Acceleration of decision tree searching for IP traffic classificationYan Luo, Ke Xiang, Sanping Li. 40-49 [doi]
- Efficient regular expression evaluation: theory to practiceMichela Becchi, Patrick Crowley. 50-59 [doi]
- A scalable multithreaded L7-filter design for multi-core serversDanhua Guo, Guangdeng Liao, Laxmi N. Bhuyan, Bin Liu, Jianxun Jason Ding. 60-68 [doi]
- On runtime management in multi-core packet processing systemsQiang Wu, Tilman Wolf. 69-78 [doi]
- MultiLayer processing - an execution model for parallel stateful packet processingJavier VerdĂș, Mario Nemirovsky, Mateo Valero. 79-88 [doi]
- BRICK: a novel exact active statistics counter architectureNan Hua, Bill Lin, Jun (Jim) Xu, Haiquan (Chuck) Zhao. 89-98 [doi]
- Packet prediction for speculative cut-through switchingPaul Congdon, Matthew Farrens, Prasant Mohapatra. 99-108 [doi]
- A programmable architecture for scalable and real-time network traffic measurementsFaisal Khan, Lihua Yuan, Chen-Nee Chuah, Soheil Ghiasi. 109-118 [doi]
- Adaptive scheduling to maximize NIC throughput in a COTS routerQinghua Ye, Mike H. MacGregor. 119-120 [doi]
- Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithmKrishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan. 121-122 [doi]
- SimNP: a flexible platform for the simulation of a network processing systemDavid Bermingham, Liu Zhen, Xiaojun Wang. 123-124 [doi]
- Towards effective network algorithms on multi-core network processorsYaxuan Qi, Zongwei Zhou, Baohua Yang, Fei He, Yibo Xue, Jun Li. 125-126 [doi]
- Performing time-sensitive network experimentsNeda Beheshti, Yashar Ganjali, Monia Ghobadi, Nick McKeown, Jad Naous, Geoff Salmon. 127-128 [doi]
- Data path credentials for high-performance capabilities-based networksTilman Wolf. 129-130 [doi]
- Low power architecture for high speed packet classificationAlan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu. 131-140 [doi]
- Stateful hardware decompression in networking environmentHao Yu, Hubertus Franke, Giora Biran, Amit Golander, Terry Nelms, Brian M. Bass. 141-150 [doi]
- On design of bandwidth scheduling algorithms for multiple data transfers in dedicated networksYunyue Lin, Qishi Wu. 151-160 [doi]
- Software techniques to improve virtualized I/O performance on multi-core systemsGuangdeng Liao, Danhua Guo, Laxmi N. Bhuyan, Steve R. King. 161-170 [doi]
- Design optimization of a highly parallel InfiniBand host channel adapterFlorian Auernhammer, Patricia Sagmeister. 171-180 [doi]