Abstract is missing.
- Automating Reconfiguration Chain Generation for SRL-Based Run-Time ReconfigurationKarel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt. 1-12 [doi]
- Architecture-Aware Reconfiguration-Centric Floorplanning for Partial ReconfigurationKizheppatt Vipin, Suhaib A. Fahmy. 13-25 [doi]
- Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory ArrayLuzhou Wang, Kentaro Sano, Satoru Yamamoto. 26-39 [doi]
- Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable ArchitectureYongjoo Kim, Jongeun Lee, JinYong Lee, Toan X. Mai, Ingoo Heo, Yunheung Paek. 40-52 [doi]
- Table-Based Division by Small Integer ConstantsFlorent de Dinechin, Laurent-Stéphane Didier. 53-63 [doi]
- Heterogeneous Systems for Energy Efficient Scientific ComputingQiang Liu, Wayne Luk. 64-75 [doi]
- The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable PlatformsS. Arash Ostadzadeh, Roel Meeuws, Imran Ashraf, Carlo Galuzzi, Koen Bertels. 76-88 [doi]
- PPMC: A Programmable Pattern Based Memory ControllerTassadaq Hussain, Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé. 89-101 [doi]
- A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core ProcessorFakhar Anjam, Quan Kong, Roel Seedorf, Stephan Wong. 102-113 [doi]
- Boosting Single Thread Performance in Mobile Processors via Reconfigurable AccelerationGeoffrey Ndu, Jim D. Garside. 114-125 [doi]
- Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAsGang Zhou, Li Li 0027, Harald Michalik. 126-137 [doi]
- ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAsShinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise. 138-150 [doi]
- Scalable Memory Hierarchies for Embedded Manycore SystemsSen Ma, Miaoqing Huang, Eugene Cartwright, David L. Andrews. 151-162 [doi]
- Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate ArraysTakahiro Watanabe, Minoru Watanabe. 163-173 [doi]
- A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic ClustersWei Ting Loke, Yajun Ha. 174-186 [doi]
- Multi-level Customisation Framework for Curve Based Monte Carlo Financial SimulationsQiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston. 187-201 [doi]
- A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPUHiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura. 202-214 [doi]
- Cost Effective Implementation of Flux Limiter Functions Using Partial ReconfigurationMohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. 215-226 [doi]
- Parallel Tempering MCMC Acceleration Using Reconfigurable HardwareGrigorios Mingas, Christos-Savvas Bouganis. 227-238 [doi]
- A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue ProblemAbid Rafique, Nachiket Kapre, George A. Constantinides. 239-250 [doi]
- Optimising Performance of Quadrature Methods with Reduced PrecisionAnson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk. 251-263 [doi]
- Teaching Hardware/Software Codesign on a Reconfigurable Computing PlatformMarkus Weinhardt. 264-275 [doi]
- Securely Sealing Multi-FPGA SystemsTim Güneysu, Igor L. Markov, André Weimerskirch. 276-289 [doi]
- FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-CoresXuan You Tan, David Boland, George A. Constantinides. 290-301 [doi]
- High Performance Reconfigurable Architecture for Double Precision Floating Point DivisionManish Kumar Jaiswal, Ray C. C. Cheung. 302-313 [doi]
- A Modular-Based Assembly Framework for Autonomous Reconfigurable SystemsTannous Frangieh, Richard Stroop, Peter Athanas, Teresa Cervero. 314-319 [doi]
- Constructing Cluster of Simple FPGA Boards for Cryptologic ComputationsYarkin Doröz, Erkay Savas. 320-328 [doi]
- Reconfigurable Multicore Architecture for Dynamic Processor ReallocationAnnie Avakian, Natwar Agrawal, Ranga Vemuri. 329-334 [doi]
- Efficient Communication for FPGA ClustersStewart Denholm, Kuen Hung Tsoi, Peter Pietzuch, Wayne Luk. 335-341 [doi]
- Performance Analysis of Reconfigurable Processors Using MVA AnalysisEhsan Zadkhosh, Sepide Fatahi, Mahmood Ahmadi. 342-349 [doi]
- PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAsRuining He, Guoqiang Liang, Yuchun Ma, Yu Wang 0002, Jinian Bian. 350-356 [doi]
- A Connection Router for the Dynamic Reconfiguration of FPGAsElias Vansteenkiste, Karel Bruneel, Dirk Stroobandt. 357-364 [doi]
- R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-ChipHongbing Fan, Yue-Ang Chen, Yu-Liang Wu. 365-371 [doi]
- Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA PlatformsKashif Latif, M. Muzaffar Rao, Athar Mahboob, Arshad Aziz. 372-378 [doi]
- CRAIS: A Crossbar Based Adaptive Interconnection SchemeChao Wang, Xi Li, Xuehai Zhou, Xiaojing Feng. 379-384 [doi]