Table of Contents

• The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data CentresChristoforos Kachris, Dimitrios Soudris, Georgi Gaydadjiev, Huy Nam Nguyen, Dimitrios S. Nikolopoulos, Angelos Bilas, Neil Morgan, Christos Strydis, Christos Tsalidis, John Balafas, Ricardo Jiménez-Peris, Alexandre Almeida. 3-13 [doi]
• A Design Methodology for the Next Generation Real-Time Vision ProcessorsJones Yudi Mori, André Werner, Arij Shallufa, Florian Fricke, Michael Hübner. 14-25 [doi]
• EEG Feature Extraction Accelerator Enabling Long Term Epilepsy Monitoring Based on Ultra Low Power WSNsEvangelinos P. Mariatos, Christos P. Antonopoulos, Nikolaos S. Voros. 26-37 [doi]
• Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion ApplicationJosé L. Núñez-Yañez. 41-53 [doi]
• An Efficient Hardware Architecture for Block Based Image Processing AlgorithmsTomasz Kryjak, Marek Gorgon, Mateusz Komorkiewicz. 54-65 [doi]
• An FPGA Stereo Matching Processor Based on the Sum of Hamming DistancesAbiel Aguilar-González, Miguel O. Arias-Estrada. 66-77 [doi]
• FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOGColm Kelly, Fahad Manzoor Siddiqui, Burak Bardak, Yun Wu, Roger F. Woods, Karen Rafferty. 78-90 [doi]
• A Comparison of Machine Learning Classifiers for FPGA Implementation of HOG-Based Human DetectionMasahito Oishi, Yoshiki Hayashida, Ryo Fujita, Yuichiro Shibata, Kiyoshi Oguri. 91-104 [doi]
• A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image ClassificationShaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip Leong, Yu Peng. 105-116 [doi]
• A Redundant Design Approach with Diversity of FPGA Resource MappingYudai Shirakura, Taisei Segawa, Yuichiro Shibata, Kenichi Morimoto, Masaharu Tanaka, Masanori Nobe, Hidenori Maruta, Fujio Kurokawa. 119-131 [doi]
• Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft ErrorsJorge Tonfat, Lucas A. Tambara, André Santos, Fernanda Gusmão de Lima Kastensmidt. 132-143 [doi]
• Low Cost Dynamic Scrubbing for Real-Time SystemsLeonardo P. Santos, Gabriel L. Nazar, Luigi Carro. 144-156 [doi]
• Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGAMohammad Tahghighi, Sharad Sinha, Wei Zhang. 159-170 [doi]
• New Partitioning Approach for Hardware Trojan Detection Using Side-Channel MeasurementsKarim M. Abdellatif, Christian Cornesse, Jacques J. A. Fournier, Bruno Robisson. 171-182 [doi]
• A Comprehensive Set of Schemes for PUF Response GenerationBilal Habib, Kris Gaj. 183-194 [doi]
• Design and Optimization of Digital Circuits by Artificial Evolution Using Hybrid Multi Chromosome Cartesian Genetic ProgrammingVitor Coimbra, Marcus Vinicius Lamar. 195-206 [doi]
• A Multi-codec Framework to Enhance Data Channels in FPGA Streaming SystemsMarlon Wijeyasinghe, David Thomas. 207-219 [doi]
• Reconfigurable FPGA-Based FFT Processor for Cognitive Radio ApplicationsMário Lopes Ferreira, Amin Barahimi, João Canas Ferreira. 223-232 [doi]
• Real-Time Audio Group Delay Correction with FFT Convolution on FPGAArthur Spierer, Andres Upegui. 233-244 [doi]
• Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement AlgorithmMarkus Weinhardt. 245-257 [doi]
• Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous SystemJeckson Dellagostin Souza, João Victor Gomes Cachola, Luigi Carro, Mateus Beck Rutzig, Antonio Carlos Schneider Beck. 261-272 [doi]
• Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore ArchitecturesFalco K. Bapp, Oliver Sander, Timo Sandmann, Hannes Stoll, Jürgen Becker. 273-286 [doi]
• Zynq Cluster for CFD Parametric SurveyNaru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. 287-299 [doi]
• Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP BlocksKonrad Häublein, Christian Hartmann, Marc Reichenbach, Dietmar Fey. 303-311 [doi]
• Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware ArchitectureMahnaz Mohammadi, Rohit Ronge, Sanjay S. Singapuram, S. K. Nandy. 312-319 [doi]
• FPGA-Based Acceleration of Pattern Matching in YARAShreyas G. Singapura, Yi-Hua E. Yang, Anand Panangadan, Tamás Németh, Peter Ng, Viktor K. Prasanna. 320-327 [doi]
• Efficient Camera Input System and Memory Partition for a Vision Soft-ProcessorJones Yudi Mori, Frederik Kautz, Michael Hübner. 328-333 [doi]
• A Lost Cycles Analysis for Performance Prediction using High-Level SynthesisBruno da Silva, Jan Lemeire, An Braeken, Abdellah Touhafi. 334-342 [doi]
• A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core SystemsCarsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker. 343-351 [doi]
• Adaptive Bandwidth Router for 3D Network-on-ChipsStephanie Friederich, Niclas Lehmann, Jürgen Becker. 352-360 [doi]
• Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented AcceleratorsJames J. Davis, Peter Y. K. Cheung. 361-368 [doi]