Abstract is missing.
- Towards Multicore Performance with Configurable Computing UnitsAnita Tino, Kaamran Raahemifar. 3-18 [doi]
- Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory CubeErfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini. 19-31 [doi]
- CASCADE: Congestion Aware Switchable Cycle Adaptive Deflection RouterGnaneswara Rao Jonna, Vamana Murthi Thuniki, Madhu Mutyam. 35-47 [doi]
- An Alternating Transmission Scheme for Deflection Routing Based Network-on-ChipsArmin Runge, Reiner Kolla. 48-59 [doi]
- Exzess: Hardware-Based RAM Encryption Against Physical Memory DisclosureAlexander Würstlein, Michael Gernoth, Johannes Götzfried, Tilo Müller. 60-71 [doi]
- Hardware-Assisted Context Management for Accelerator Virtualization: A Case Study with RSAYing Gao, Timothy Sherwood. 72-83 [doi]
- Adaptive Cache StructuresCarsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker. 87-99 [doi]
- Optimization of a Linked Cache Coherence Protocol for Scalable Manycore CoherenceRicardo Fernández Pascual, Alberto Ros, Manuel E. Acacio. 100-112 [doi]
- Generic Algorithmic Scheme for 2D Stencil Applications on Hybrid MachinesStéphane Vialle, Sylvain Contassot-Vivier, Patrick Mercier. 115-129 [doi]
- GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load BalancingErnst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars. 130-142 [doi]
- Task Variants with Different Scratchpad Memory Consumption in Multi-Task EnvironmentsMartin Böhnert, Christoph Scholl. 143-156 [doi]
- Feedback-Based Admission Control for Hard Real-Time Task Allocation Under Dynamic Workload on Many-Core SystemsPiotr Dziurzanski, Amit Kumar Singh, Leandro Soares Indrusiak. 157-169 [doi]
- Data Age Diminution in the Logical Execution Time ModelChristian Bradatsch, Florian Kluge, Theo Ungerer. 173-184 [doi]
- Accurate Sample Time Reconstruction for Sensor Data SynchronizationSebastian Stieber, Rainer Dorsch, Christian Haubelt. 185-196 [doi]
- DiaSys: On-Chip Trace Analysis for Multi-processor System-on-ChipPhilipp Wagner 0001, Thomas Wild, Andreas Herkersdorf. 197-209 [doi]
- Analysis of Intel's Haswell Microarchitecture Using the ECM Model and MicrobenchmarksJohannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein. 210-222 [doi]
- Measurement-Based Probabilistic Timing Analysis for Graphics Processor UnitsKostiantyn Berezovskyi, Fabrice Guet, Luca Santinelli, Konstantinos Bletsas, Eduardo Tovar. 223-236 [doi]
- Reducing Energy Consumption of Data Transfers Using Runtime Data Type ConversionMichael Bromberger, Vincent Heuveline, Wolfgang Karl. 239-250 [doi]
- Balancing High-Performance Parallelization and Accuracy in Canny Edge DetectorValery Kritchallo, Billy Braithwaite, Erik Vermij, Koen Bertels, Zaid Al-Ars. 251-262 [doi]
- Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-Based ModelingRafael Rosales, Christian Herglotz, Michael Glaß, André Kaup, Jürgen Teich. 263-276 [doi]
- Low-Cost Hardware Infrastructure for Runtime Thread Level Energy AccountingMarius Marcu, Oana Boncalo, Madalin Ghenea, Alexandru Amaricai, Jan Weinstock, Rainer Leupers, Zheng Wang, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Cosmin Cernazanu-Glavan, Lucian Bara, Marian Ionascu. 277-289 [doi]
- Reducing NoC and Memory Contention for ManycoresVishwanathan Chandru, Frank Mueller. 293-305 [doi]
- An Efficient Data Structure for Dynamic Two-Dimensional ReconfigurationSándor P. Fekete, Jan-Marc Reinhardt, Christian Scheffer. 306-318 [doi]
- Runtime Clustering of Similarly Behaving Agents in Open Organic Computing SystemsJan Kantert, Richard Scharrer, Sven Tomforde, Sarah Edenhofer, Christian Müller-Schloer. 321-333 [doi]
- Comparison of Dependency Measures for the Detection of Mutual Influences in Organic Computing SystemsStefan Rudolph, Rainer Hihn, Sven Tomforde, Jörg Hähner. 334-347 [doi]
- Augmenting the Algorithmic Structure of XCS by Means of InterpolationAnthony Stein, Dominik Rauh, Sven Tomforde, Jörg Hähner. 348-360 [doi]
- Estimation of End-to-End Packet Error Rates for NoC MulticastsMichael Vonbun, Thomas Wild, Andreas Herkersdorf. 363-374 [doi]
- Protecting Code Regions on Asymmetrically Reliable CachesSanem Arslan, Haluk Rahmi Topcuoglu, Mahmut Taylan Kandemir, Oguz Tosun. 375-387 [doi]
- A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUsSarah Azimi, Boyang Du, Luca Sterpone. 388-400 [doi]