Abstract is missing.
- Logic Decomposition of Asynchronous Circuits Using STG UnfoldingsVictor Khomenko. 3-12 [doi]
- Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level SynthesisNikolaos Andrikos, Luciano Lavagno. 13-21 [doi]
- CPlace: A Constructive Placer for Synchronous and Asynchronous CircuitsEvriklis Kounalakis, Christos P. Sotiriou. 22-29 [doi]
- Synchronizer Performance in Deep Sub-Micron TechnologySuwen Yang, Ian W. Jones, Mark R. Greenstreet. 33-42 [doi]
- GALS Design for On-chip Ground Bounce SuppressionXin Fan, Milos Krstic, Christoph Wolf, Eckhard Grass. 43-52 [doi]
- Formal Verification of C-element CircuitsChao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory. 55-64 [doi]
- Improving Dependability and Performance of Fully Asynchronous On-chip NetworksMasashi Imai, Tomohiro Yoneda. 65-76 [doi]
- Variation Tolerant AFPGA ArchitectureHock Soon Low, Delong Shang, Fei Xia, Alexandre Yakovlev. 77-86 [doi]
- A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting SystemsXuefu Zhang, Delong Shang, Fei Xia, Alexandre Yakovlev. 89-98 [doi]
- Address-Event Communication Using Token-Ring Mutual ExclusionNabil Imam, Rajit Manohar. 99-108 [doi]
- Long-Distance On-chip Communication Using GasPJo C. Ebergen, Bill Coates, Austin Lee. 109-116 [doi]