Abstract is missing.
- Compiling code accelerators for FPGAsWalid A. Najjar. 1-2 [doi]
- A fast and generic hybrid simulation approach using C virtual machineLei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 3-12 [doi]
- Compiler generation from structural architecture descriptionsFlorian Brandner, Dietmar Ebner, Andreas Krall. 13-22 [doi]
- Non-transparent debugging for software-pipelined loopsHugo Venturini, Frédéric Riss, Jean-Claude Fernandez, Miguel Santana. 23-32 [doi]
- An integrated ARM and multi-core DSP simulatorSharad Singhai, MingYung Ko, Sanjay Jinturkar, Mayan Moudgill, John Glossner. 33-37 [doi]
- SCCP/x: a compilation profile to support testing and verification of optimized codeRaimund Kirner. 38-42 [doi]
- Performance-driven syntax-directed synthesis of asynchronous processorsLuis A. Plana, Doug Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley. 43-47 [doi]
- Stack size reduction of recursive programsStefan Schäckeler, Weijia Shang. 48-52 [doi]
- Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systemsHoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim, Soonhoi Ha. 53-57 [doi]
- A hybrid code compression technique using bitmask and prefix encoding with enhanced dictionary selectionSyed Imtiaz Haider, Leyla Nazhandali. 58-62 [doi]
- Techniques for code and data management in the local stores of the cell processorKevin K. O Brien. 63-64 [doi]
- Recursive function data allocation to scratch-pad memoryAngel Dominguez, Nghi Nguyen, Rajeev Barua. 65-74 [doi]
- Fragment cache management for dynamic binary translators in embedded systems with scratchpadJosé Baiocchi, Bruce R. Childers, Jack W. Davidson, Jason Hiser, Jonathan Misurda. 75-84 [doi]
- Scratch-pad memory allocation without compiler support for java applicationsNghi Nguyen, Angel Dominguez, Rajeev Barua. 85-94 [doi]
- Towards understanding architectural tradeoffs in MEMS closed-loop feedback controlGreg Hoover, Forrest Brewer, Timothy Sherwood. 95-102 [doi]
- Application driven embedded system design: a face recognition case studyKarthik Ramani, Al Davis. 103-114 [doi]
- Hierarchical coarse-grained stream compilation for software defined radioYuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevor N. Mudge. 115-124 [doi]
- Rethinking custom ISE identification: a new processor-agnostic methodAjay K. Verma, Philip Brisk, Paolo Ienne. 125-134 [doi]
- An efficient framework for dynamic reconfiguration of instruction-set customizationHuynh Phung Huynh, Joon Edward Sim, Tulika Mitra. 135-144 [doi]
- Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platformsAndrea Marongiu, Luca Benini, Mahmut T. Kandemir. 145-149 [doi]
- Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCsChengmo Yang, Alex Orailoglu. 150-154 [doi]
- Supporting multithreading in configurable soft processor coresRoger Moussali, Nabil Ghanem, Mazen A. R. Saghir. 155-159 [doi]
- A group-based wear-leveling algorithm for large-capacity flash memory storage systemsDawoon Jung, Yoon-Hee Chae, Heeseung Jo, Jinsoo Kim, Joonwon Lee. 160-164 [doi]
- Facilitating compiler optimizations through the dynamic mapping of alternate register structuresChris Zimmer, Stephen Roderick Hines, Prasad Kulkarni, Gary S. Tyson, David B. Whalley. 165-169 [doi]
- Vertical object layout and compression for fixed heapsBen Titzer, Jens Palsberg. 170-178 [doi]
- Software controlled memory layout reorganization for irregular array access patternsDoosan Cho, Ilya Issenin, Nikil Dutt, Jonghee W. Yoon, Yunheung Paek. 179-188 [doi]
- A self-maintained memory module supporting DMMWeixing Ji, Feng Shi, Baojun Qiao. 189-197 [doi]
- Eliminating inter-process cache interference through cache reconfigurability for real-time and low-power embedded multi-tasking systemsRakesh Reddy, Peter Petrov. 198-207 [doi]
- Multicore architecturesTrevor N. Mudge. 208 [doi]
- An optimistic and conservative register assignment heuristic for chordal graphsPhilip Brisk, Ajay K. Verma, Paolo Ienne. 209-217 [doi]
- A simplified java bytecode compilation system for resource-constrained embedded processorsCarmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum. 218-228 [doi]
- A backtracking instruction scheduler using predicate-based code hoisting to fill delay slotsTom Vander Aa, Bingfeng Mei, Bjorn De Sutter. 229-237 [doi]
- INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorationsRahul Nagpal, Arvind Madan, Amrutur Bhardwaj, Y. N. Srikant. 238-247 [doi]
- Cache leakage control mechanism for hard real-time systemsJaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen. 248-256 [doi]
- Performance optimal processor throttling under thermal constraintsRavishankar Rao, Sarma B. K. Vrudhula. 257-266 [doi]
- A low power front-end for embedded processors using a block-aware instruction setAhmad Zmily, Christos Kozyrakis. 267-276 [doi]