Abstract is missing.
- Automatic generation of hardware/software interfacesArvind. 1-2 [doi]
- Low-overhead virtualization of mobile platformsGernot Heiser. 3-4 [doi]
- Selective just-in-time compilation for client-side mobile javascript engineSeong-Won Lee, Soo-Mook Moon. 5-14 [doi]
- A method-based ahead-of-time compiler for android applicationsChih-Sheng Wang, Guillermo Pérez, Yeh-Ching Chung, Wei-Chung Hsu, Wei Kuan Shih, Hong-Rong Hsu. 15-24 [doi]
- Studying optimal spilling in the light of SSAQuentin Colombet, Florian Brandner, Alain Darte. 25-34 [doi]
- An efficient heuristic for instruction scheduling on clustered vliw processorsXuemeng Zhang, Hui Wu, Jingling Xue. 35-44 [doi]
- Graph-coloring and treescan register allocation using repairingQuentin Colombet, Benoit Boissinot, Philip Brisk, Sebastian Hack, Fabrice Rastello. 45-54 [doi]
- A unified approach to eliminate memory accesses earlyMafijul Md. Islam, Per Stenström. 55-64 [doi]
- An evaluation of different modeling techniques for iterative compilationEunjung Park, Sameer Kulkarni, John Cavazos. 65-74 [doi]
- A novel thread scheduler design for polymorphic embedded systemsViswanath Krishnamurthy, Swamy D. Ponpandi, Akhilesh Tyagi. 75-84 [doi]
- Realizing near-true voltage scaling in variation-sensitive l1 caches via fault buffersTayyeb Mahmood, Soontae Kim. 85-94 [doi]
- FFT-cache: a flexible fault-tolerant cache architecture for ultra low voltage operationAbbas BanaiyanMofrad, Houman Homayoun, Nikil Dutt. 95-104 [doi]
- Smart cache cleaning: energy efficient vulnerability reduction in embedded processorsReiley Jeyapaul, Aviral Shrivastava. 105-114 [doi]
- Architecting processors to allow voltage/reliability tradeoffsJohn Sartori, Rakesh Kumar. 115-124 [doi]
- Cost-effective safety and fault localization using distributed temporal redundancyBrett H. Meyer, Benton H. Calhoun, John Lach, Kevin Skadron. 125-134 [doi]
- Stochastic computing: embracing errors in architectureand design of processors and applicationsJohn Sartori, Joseph Sloan, Rakesh Kumar. 135-144 [doi]
- WCET-driven cache-aware code positioningHeiko Falk, Helena Kotthaus. 145-154 [doi]
- Enabling parametric feasibility analysis in real-time calculus driven performance evaluationAlena Simalatsar, Yusi Ramadian, Kai Lampka, Simon Perathoner, Roberto Passerone, Lothar Thiele. 155-164 [doi]
- WCET-driven branch prediction aware code positioningSascha Plazar, Jan C. Kleinsorge, Heiko Falk, Peter Marwedel. 165-174 [doi]
- A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCsAmit Kumar Singh, Akash Kumar, Thambipillai Srikanthan. 175-184 [doi]
- Evaluation of an accelerator architecture for speckle reducing anisotropic diffusionSiddharth Nilakantan, Srikanth Annangi, Nikhil Gulati, Karthik Sangaiah, Mark Hempstead. 185-194 [doi]
- An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architectureRicardo S. Ferreira, Julio C. Goldner Vendramini, Lucas Mucida, Monica Magalhães Pereira, Luigi Carro. 195-204 [doi]
- Localizing globals and statics to make C programs thread-safeAdam R. Smith, Prasad A. Kulkarni. 205-214 [doi]
- Vector class on limited local memory (LLM) multi-core processorsKe Bai, Di Lu, Aviral Shrivastava. 215-224 [doi]
- System-level modeling and synthesis of flow-based microfluidic biochipsWajid Hassan Minhass, Paul Pop, Jan Madsen. 225-234 [doi]
- Hardware/software architecture for flash memory storage systemsSang Lyul Min, Eyee Hyun Nam. 235-236 [doi]
- Compositional analysis of real-time embedded systemsLinh T. X. Phan, Insup Lee, Oleg Sokolsky. 237-238 [doi]