Abstract is missing.
- Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case studyHaris Javaid, Sri Parameswaran. 1-6 [doi]
- Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-designGiovanni Beltrame, Luca Fossati, Donatella Sciuto. 7-12 [doi]
- A time-predictable system initialization design for huge-capacity flash-memory storage systemsChin-Hsien Wu. 13-18 [doi]
- Deterministic service guarantees for nand flash using partial block cleaningSiddharth Choudhuri, Tony Givargis. 19-24 [doi]
- Static analysis of processor stall cycle aggregationJongeun Lee, Aviral Shrivastava. 25-30 [doi]
- Application specific non-volatile primary memory for embedded systemsKwangyoon Lee, Alex Orailoglu. 31-36 [doi]
- Scratchpad allocation for concurrent embedded softwareVivy Suhendra, Abhik Roychoudhury, Tulika Mitra. 37-42 [doi]
- Software optimization for MPSoC: a mpeg-2 decoder case studyEric Cheung, Harry Hsieh, Felice Balarin. 43-48 [doi]
- Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuitsLance Saldanha, Roman L. Lysecky. 49-54 [doi]
- A performance-oriented hardware/software partitioning for datapath applicationsLaura Frigerio, Fabio Salice. 55-60 [doi]
- Traversal caches: a first step towards FPGA acceleration of pointer-based data structuresGreg Stitt, Gaurav Chaudhari, James Coole. 61-66 [doi]
- Specification and OS-based implementation of self-adaptive, hardware/software embedded systemsYvan Eustache, Jean-Philippe Diguet. 67-72 [doi]
- Distributed and low-power synchronization architecture for embedded multiprocessorsChenjie Yu, Peter Petrov. 73-78 [doi]
- LOCS: a low overhead profiler-driven design flow for security of MPSoCsKrutartha Patel, Sri Parameswaran. 79-84 [doi]
- Online adaptive utilization control for real-time embedded multiprocessor systemsJianguo Yao, Xue Liu, Mingxuan Yuan, Zonghua Gu. 85-90 [doi]
- Intra- and inter-processor hybrid performance modeling for MPSoC architecturesFrank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal. 91-96 [doi]
- Dynamic tuning of configurable architectures: the AWW online algorithmChen Huang, David Sheldon, Frank Vahid. 97-102 [doi]
- Static analysis for fast and accurate design space exploration of cachesYun Liang, Tulika Mitra. 103-108 [doi]
- Profiling of lossless-compression algorithms for a novel biomedical-implant architectureChristos Strydis, Georgi Gaydadjiev. 109-114 [doi]
- Holistic design and caching in mobile computingMwaffaq Otoom, JoAnn M. Paul. 115-120 [doi]
- You can catch more bugs with transaction level honeyMiron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin. 121-124 [doi]
- Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICsJohn P. Grossman, Cliff Young, Joseph A. Bank, Kenneth Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw. 125-130 [doi]
- Model checking SystemC designs using timed automataPaula Herber, Joachim Fellmuth, Sabine Glesner. 131-136 [doi]
- Specification-based compaction of directed tests for functional validation of pipelined processorsHeon-Mo Koo, Prabhat Mishra. 137-142 [doi]
- Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluationMatthias Krause, Dominik Englert, Oliver Bringmann, Wolfgang Rosenstiel. 143-148 [doi]
- Cache-aware optimization of BAN applicationsYun Liang, Lei Ju, Samarjit Chakraborty, Tulika Mitra, Abhik Roychoudhury. 149-154 [doi]
- Don t forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAsDavid Sheldon, Frank Vahid. 155-160 [doi]
- Reliable performance analysis of a multicore multithreaded system-on-chipSimon Schliecker, Mircea Negrean, Gabriela Nicolescu, Pierre G. Paulin, Rolf Ernst. 161-166 [doi]
- Extending open core protocol to support system-level cache coherenceKonstantinos Aisopos, Chien-Chun Chou, Li-Shiuan Peh. 167-172 [doi]
- Performance debugging of Esterel specificationsLei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samarjit Chakraborty. 173-178 [doi]
- SPaC: a symbolic pareto calculatorHamid Shojaei, Twan Basten, Marc Geilen, Phillip Stanley-Marbell. 179-184 [doi]
- Providing accurate event models for the analysis of heterogeneous multiprocessor systemsSimon Schliecker, Jonas Rox, Matthias Ivers, Rolf Ernst. 185-190 [doi]
- Highly-cited ideas in system codesign and synthesisFrank Vahid, Tony Givargis. 191-196 [doi]
- A security monitoring service for NoCsLeandro Fiorin, Gianluca Palermo, Cristina Silvano. 197-202 [doi]
- ODOR: a microresonator-based high-performance low-cost router for optical networks-on-ChipHuaxi Gu, Jiang Xu, Zheng Wang. 203-208 [doi]
- Asynchronous transient resilient links for NoCSimon Ogg, Bashir M. Al-Hashimi, Alexandre Yakovlev. 209-214 [doi]
- Distributed flit-buffer flow control for networks-on-chipNicola Concer, Michele Petracca, Luca P. Carloni. 215-220 [doi]
- Co-design in the wildernessDan J. Gale. 221-222 [doi]
- Design and defect tolerance beyond CMOSXiaobo Sharon Hu, Alexander Khitun, Konstantin K. Likharev, Michael T. Niemier, Mingqiang Bao, Kang L. Wang. 223-230 [doi]
- Slack analysis in the system design loopGirish Venkataramani, Seth Copen Goldstein. 231-236 [doi]
- Symbolic voter placement for dependability-aware system synthesisFelix Reimann, Michael Glabeta, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich. 237-242 [doi]
- Speculative DMA for architecturally visible storage in instruction set extensionsTheo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon. 243-248 [doi]
- Yield maximization for system-level task assignment and configuration selection of configurable multiprocessorsLove Singhal, Sejong Oh, Eli Bozorgzadeh. 249-254 [doi]
- Methodology for multi-granularity embedded processor power model generation for an ESL design flowYoung-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt. 255-260 [doi]
- Power reduction via macroblock prioritization for power aware H.264 video applicationsMichael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li. 261-266 [doi]
- Guaranteed scheduling for repetitive hard real-time tasks under the maximal temperature constraintGang Quan, Yan Zhang, William Wiles, Pei Pei. 267-272 [doi]
- System-level mitigation of WID leakage power variability using body-bias islandsSiddharth Garg, Diana Marculescu. 273-278 [doi]