Abstract is missing.
- High-Performance low-vcc in-order coreJaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González. 1-11 [doi]
- Architecting for power management: The IBM POWER7:::TM::: approachMalcolm S. Ware, Karthick Rajamani, Michael S. Floyd, Bishop Brock, Juan C. Rubio, Freeman L. Rawson III, John B. Carter. 1-11 [doi]
- StimulusCache: Boosting performance of chip multiprocessors with excess cacheHyunjin Lee, Sangyeun Cho, Bruce R. Childers. 1-12 [doi]
- ESP-NUCA: A low-cost adaptive Non-Uniform Cache ArchitectureJavier Merino, Valentin Puente, José-Ángel Gregorio. 1-10 [doi]
- DMA++: on the fly data realignment for on-chip memoriesNikola Vujic, Marc González, Felipe Cabarcas, Alex Ramírez, Xavier Martorell, Eduard Ayguadé. 1-12 [doi]
- UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them allBogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, Anne Bracy. 1-12 [doi]
- Explaining cache SER anomaly using DUE AVF measurementArijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Athanasios E. Papathanasiou, Mike Plaster, Norbert Seifert. 1-12 [doi]
- Is hardware innovation over?Arvind. 1 [doi]
- DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performanceDan Tang, Yungang Bao, Weiwu Hu, Mingyu Chen. 1-12 [doi]
- A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvementGuangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li. 1-12 [doi]
- Scalable architectural support for trusted softwareDavid Champagne, Ruby B. Lee. 1-12 [doi]
- Graphite: A distributed parallel simulator for multicoresJason E. Miller, Harshad Kasture, George Kurian, Charles Gruenwald III, Nathan Beckmann, Christopher Celio, Jonathan Eastep, Anant Agarwal. 1-12 [doi]
- FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbarYan Pan, John Kim, Gokhan Memik. 1-12 [doi]
- LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicoresBrian Greskamp, Ulya R. Karpuzcu, Josep Torrellas. 1-12 [doi]
- An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidthDong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, Hsien-Hsin S. Lee. 1-12 [doi]
- Towards scalable, energy-efficient, bus-based on-chip networksAniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian. 1-12 [doi]
- Delay-Hiding energy management mechanisms for DRAMMingsong Bi, Ran Duan, Chris Gniady. 1-10 [doi]
- Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performanceFang Liu, Xiaowei Jiang, Yan Solihin. 1-12 [doi]
- Improving read performance of Phase Change Memories via Write Cancellation and Write PausingMoinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño. 1-11 [doi]
- HARE: Hardware assisted reverse executionIoannis Doudalis, Milos Prvulovic. 1-12 [doi]
- Extreme scale computing: Challenges and opportunitiesJosep Torrellas, Bill Gropp, Vivek Sarkar, Jaime Moreno, Kunle Olukotun. 1 [doi]
- SIF: Overcoming the limitations of SIMD devices via implicit permutationLibo Huang, Li Shen, Zhiying Wang, Wei Shi, Nong Xiao, Sheng Ma. 1-12 [doi]
- ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllersYoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter. 1-12 [doi]
- Handling branches in TLS systems with Multi-Path ExecutionPolychronis Xekalakis, Marcelo Cintra. 1-12 [doi]
- Worth their watts? - an empirical study of datacenter serversArunchandar Vasan, Anand Sivasubramaniam, Vikrant Shimpi, T. Sivabalan, Rajesh Subbiah. 1-10 [doi]
- Value Based BTB Indexing for indirect jump predictionMuhammad Umar Farooq, Lei Chen, Lizy Kurian John. 1-11 [doi]
- Operating system support for overlapping-ISA heterogeneous multi-core architecturesTong Li, Paul Brett, Rob C. Knauerhase, David A. Koufaty, Dheeraj Reddy, Scott Hahn. 1-12 [doi]
- A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systemsDimitris Kaseridis, Jeffrey Stuecheli, Jian Chen, Lizy Kurian John. 1-11 [doi]
- Application performance modeling in a virtualized environmentSajib Kundu, Raju Rangaswami, Kaushik Dutta, Ming Zhao. 1-10 [doi]
- Simple virtual channel allocation for high throughput and high frequency on-chip routersYi Xu, Bo Zhao, Youtao Zhang, Jun Yang 0002. 1-11 [doi]
- BOLT: Energy-efficient Out-of-Order Latency-Tolerant executionAndrew D. Hilton, Amir Roth. 1-12 [doi]
- High performance network virtualization with SR-IOVYaozu Dong, Xiaowei Yang, Xiaoyong Li, Jianhui Li, Kun Tian, Haibing Guan. 1-10 [doi]
- IADVS: On-demand performance for interactive applicationsMingsong Bi, Igor Crk, Chris Gniady. 1-10 [doi]
- Exascale computing: The challenges and opportunities in the next decadeTilak Agerwala. 1 [doi]
- LiteTM: Reducing transactional state overheadSyed Ali Raza Jafri, Mithuna Thottethodi, T. N. Vijaykumar. 1-12 [doi]
- Interval simulation: Raising the level of abstraction in architectural simulationDavy Genbrugge, Stijn Eyerman, Lieven Eeckhout. 1-12 [doi]
- COMIC++: A software SVM system for heterogeneous multicore accelerator clustersJaejin Lee, Jun Lee, Sangmin Seo, Jungwon Kim, Seungkyun Kim, Zehra Sura. 1-12 [doi]
- CHOP: Adaptive filter-based DRAM caching for CMP server platformsXiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian. 1-12 [doi]
- Designing a processor from the ground up to allow voltage/reliability tradeoffsAndrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori. 1-11 [doi]