Abstract is missing.
- Using Transformations and Verification in Ciruit DesignJames B. Saxe, Stephen J. Garland, John V. Guttag, James J. Horning. 1-25
- Modulo-N Counters: Design and Analysis of Delay-Insensitive CircuitsJo C. Ebergen, Ad M. G. Peeters. 27-46
- Newtonian Arbiters Cannot be Proven CorrectMichael Mendler, Terry Stroup. 47-66
- Incomplete TRS-Specifications of Boolean Functions and their VerificationStefan Krischer. 67-79
- Using the Language Lustre for Sequential Circuit VerificationGhislaine Thuau, Bachir Berkane. 81-96
- Invited talk: Three Notions of ProofPeter Naur. 97-101
- Transe: An Experimental Transformation Assistant for Digital Circuit DesignGuy Durrieu, Kamel Kessaci, Michel Lemaître. 103-118
- Circuit Analysis by Non-Standard InterpretationSatnam Singh. 119-138
- Reasoning about Permutations in Regular ArraysBjörn Lisper, Sanjay V. Rajopadhye. 139-157
- Sequence Semantics of RubyLars Rossen, Robin Sharp. 159-171
- A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALUDiederik Verkest, Luc J. M. Claesen, Hugo De Man. 173-192
- Invited Talk: Formal Design in an Industrial Research Laboratory: Lessons and PerspectivesJörg Bormann, H. Nusser-Wehlan, Gerd Venzl. 193-213
- Using Synchronized Transitions for Simulation and Timing VerificationMark R. Greenstreet. 215-236
- Provably Correct Synthesis of Asynchronous CircuitsScott F. Smith, Amy E. Zwarico. 237-260
- High-Level Design of an Asynchronous Packet-Routing ChipMark B. Josephs, Rudolf H. Mak, Jan Tijmen Udding, Tom Verhoeff, Jelio T. Yantchev. 261-274
- Analysis and Identification of Self-Timed CircuitsMichael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky. 275-287