Abstract is missing.
- Bitfile preservation - Generation of reusable out of context modulesChristian Stullein, Norbert Abel, Udo Kebschull. 1-6 [doi]
- Hardware/software co-compilation with the Nymble systemJens Huthmann, Björn Liebig, Julian Oppermann, Andreas Koch 0001. 1-8 [doi]
- On a FPGA-based method for authentication using Edwards curvesAndré Himmighofen, Bernhard Jungk, Steffen Reith. 1-7 [doi]
- An exploration of heterogeneous systemsJesus Carabano, Francisco Dios, Masoud Daneshtalab, Masoumeh Ebrahimi. 1-7 [doi]
- The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGAFrancesco Robino, Johnny Öberg. 1-8 [doi]
- A new model for estimating bit error probabilities of Ring-Oscillator PUFsMatthias Hiller, Georg Sigl, Michael Pehl. 1-8 [doi]
- SoC performance evaluation with ArchC and TLM-2.0Jorg Walter, Jorg Lenhardt, Wolfram Schiffmann. 1-8 [doi]
- Towards a Configurable Many-core Accelerator for FPGA-based embedded systemsMarco Ramírez, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila. 1-4 [doi]
- Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDLSimen Gimle Hansen, Dirk Koch, Jim Torresen. 1-8 [doi]
- An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architectureVianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet. 1-8 [doi]
- Shared hardware accelerator architectures for heterogeneous MPSoCsDamak Bouthaina, Mouna Baklouti, Smaïl Niar, Mohamed Abid. 1-6 [doi]
- RecMIN: A reconfiguration architecture for network on chipAlexander Logvinenko, Carsten Gremzow, Dietmar Tutsch. 1-6 [doi]
- Approximation of hyperbolic tangent activation function using hybrid methodsMaicon A. Sartin, Alexandre C. R. da Silva. 1-6 [doi]
- Dynamically reconfigurable FIR filter architectures with fast reconfigurationMartin Kumm, Konrad Moller, Peter Zipf. 1-8 [doi]
- Exploiting FPGA block memories for protected cryptographic implementationsShivam Bhasin, Wei He, Sylvain Guilley, Jean-Luc Danger. 1-8 [doi]
- Measuring memory access latency for software objects in a NUMA system-on-chip architectureDaniela Genius. 1-8 [doi]
- Centralized traffic monitoring for online-resizable clusters in Networks-on-ChipPhilipp Gorski, Dirk Timmermann. 1-8 [doi]
- A parallelization methodology for reconfigurable systems applied to edge detectionJuan M. Campos, René Cumplido, Claudia Feregrino Uribe, Roberto Perez-Andrade. 1-7 [doi]
- Memory allocation and optimization in system-level architectural synthesisShuo Li, Ahmed Hemani. 1-7 [doi]
- ACMA: Accuracy-configurable multiplier architecture for error-resilient System-on-ChipKartikeya Bhardwaj, Pravin S. Mane. 1-6 [doi]
- Dynamic task remapping for power and latency performance improvement in priority-based non-preemptive Networks On ChipJames Harbin, Leandro Soares Indrusiak. 1-7 [doi]
- A framework for effective exploitation of partial reconfiguration in dataflow computingRiccardo Cattaneo, Xinyu Niu, Christian Pilato, Tobias Becker, Wayne Luk, Marco D. Santambrogio. 1-8 [doi]
- D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systemsFabio Cancare, Christian Pilato, Andrea Cazzaniga, Donatella Sciuto, Marco D. Santambrogio. 1-6 [doi]
- Component based design using constraint programming for module placement on FPGAsAlexander Wold, Dirk Koch, Jim Torresen. 1-8 [doi]
- An FPGA design and implementation framework combined with commercial VLSI CADsQian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 1-7 [doi]
- Register allocation for high-level synthesis of hardware accelerators targeting FPGAsGerald Hempel, Jan Hoyer, Thilo Pionteck, Christian Hochberger. 1-6 [doi]
- CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP designJuan Fernando Eusse, Christopher Williams, Rainer Leupers. 1-8 [doi]
- A programmable FPGA-based cryptoprocessor for bilinear pairings over F2mEduardo Cuevas-Farfan, Miguel Morales-Sandoval, René Cumplido, Claudia Feregrino Uribe, Ignacio Algredo-Badillo. 1-8 [doi]
- Practical measurements of data path delays for IP authentication & integrity verificationIngrid Exurville, Jacques Fournier, Jean-Max Dutertre, Bruno Robisson, Assia Tria. 1-6 [doi]
- Addiguration: Exploring configuration behavior of Spartan-3 devicesMichael Dreschmann, Oliver Sander, Alexander Klimm, Christoph Roth, Jürgen Becker. 1-6 [doi]
- Improving parallel MPSoC simulation performance by exploiting dynamic routing delay predictionChristoph Roth, Harald Bucher, Simon Reder, Oliver Sander, Jürgen Becker. 1-8 [doi]
- Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCsAnup Das, Amit Kumar Singh, Akash Kumar. 1-7 [doi]
- Reconciling application power control and operating systems for optimal power and performanceDominic Hillenbrand, Yuuki Furuyama, Akihiro Hayashi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara. 1-8 [doi]
- Among slow dwarfs and fast giants: A systematic design space exploration of KECCAKBernhard Jungk, Marc Stöttinger. 1-8 [doi]
- Flexible, ultra-low power sensor nodes through configurable finite state machinesJuan Carlos Pena Ramos, Marian Verhelst. 1-7 [doi]