Abstract is missing.
- Rapid prototyping and compact testing of CPU emulatorsWeiqin Ma, A. Forin, Jyh-Charn Liu. 1-7 [doi]
- Fine grain analysis of simulators accuracy for calibrating performance modelsMarco Lattuada, Fabrizio Ferrandi. 1-7 [doi]
- Counter Embedded Memory architecture for trusted computing platformGavin Xiaoxu Yao, Ray C. C. Cheung, Kim-Fung Man. 1-7 [doi]
- Embedded systems virtualization: The next challenge?Alexandra Aguiar, Fabiano Hessel. 1-7 [doi]
- Host-compiled simulation of multi-core platformsAndreas Gerstlauer. 1-6 [doi]
- Rapid prototyping for digital signal processing systems using Parameterized Synchronous Dataflow graphsHsiang-Huang Wu, Hojin Kee, Nimish Sane, William Plishker, Shuvra S. Bhattacharyya. 1-7 [doi]
- Exploring SW performance using preemptive RTOS modelsGunar Schirner. 1-7 [doi]
- Host-compiled simulation of multi-core platformsAndreas Gerstlauer. 1-6 [doi]
- Automated synthesis of Time-Triggered Architecture-based TrueTime models for platform effects simulation and analysisGraham Hemingway, Joseph Porter, Nicholas Kottenstette, Harmon Nine, Christopher P. van Buskirk, Gabor Karsai, Janos Sztipanovits. 1-7 [doi]
- Umple: Towards combining model driven with prototype driven system developmentAndrew Forward, Omar Bahy Badreddin, Timothy C. Lethbridge. 1-7 [doi]
- Reconfigurable router for dynamic Networks-on-ChipPhilipp Mahr, Christophe Bobda. 1-6 [doi]
- Performance-cost analyses software for H.264 Forward/Inverse Integer TransformTrang T. T. Do, Thinh M. Le, Binh P. Nguyen, Yajun Ha. 1-7 [doi]
- Scenario path identification for distributed systems: A graph based approachAnanya Kanjilal, Sabnam Sengupta, S. Bhattacharya. 1-8 [doi]
- Failure mode and effect analysis based on electric and electronic architectures of vehicles to support the safety lifecycle ISO/DIS 26262Martin Hillenbrand, Matthias Heinz, Nico Adler, Johannes Matheis, Klaus D. Müller-Glaser. 1-7 [doi]
- An FPGA based semi-parallel architecture for higher order Moving Target Indication (MTI) processingZulfiqar Ali, Ali Arshad, Umair Razzaq. 1-7 [doi]
- An efficient hierarchical router for large 3D NoCsW. Lafi, Didier Lattard, Ahmed Amine Jerraya. 1-5 [doi]
- Embedded system environment: A framework for TLM-based design and prototypingSamar Abdi, Yonghyun Hwang, Lochi Yu, Hansu Cho, Ines Viskic, Daniel D. Gajski. 1-7 [doi]
- Performance evaluation for passive-type Optical network-on-chipAtef Allam, Ian O Connor, W. Heirman. 1-7 [doi]
- Automatic modulation classification for rapid radio deploymentAdolfo Recio, Jorge Alberto Surís, Peter Athanas. 1-7 [doi]
- Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chipBruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin, Pierre G. Paulin. 1-9 [doi]
- Highly efficient forward two-dimensional DCT module architecture for H.264/SVCRonaldo Husemann, Mariano Majolo, Valter Roesler, José Valdeni de Lima, Altamiro Amadeu Susin. 1-7 [doi]
- An approach for rapidly adapting the demands of ISO/DIS 26262 to electric/electronic architecture modelingMartin Hillenbrand, Matthias Heinz, Klaus D. Müller-Glaser, Nico Adler, Johannes Matheis, Clemens Reichmann. 1-7 [doi]
- MpAssign: A framework for solving the many-core platform mapping problemYoucef Bouchebaba, Pierre G. Paulin, A. E. Ozcan, Bruno Lavigueur, Michel Langevin, Olivier Benny, Gabriela Nicolescu. 1-7 [doi]
- Validating quality attribute requirements via execution-based model checkingDoron Drusinsky, Man-tak Shing. 1-7 [doi]
- Rapid specification of hardware-in-the-loop test systems in the automotive domain based on the electric / electronic architecture description of, vehiclesMartin Hillenbrand, Matthias Heinz, Klaus D. Müller-Glaser. 1-6 [doi]